What to Expect at the VLSI Technology Symposium

Article By : Don Scansen

The papers from the upcoming VLSI Technology Symposium suggest there's some agreement on general direction, but little agreement on terminology.

The VLSI 2021 Symposia (plural, since there’s a semiconductor technology track and a circuits & systems track) will be a virtual event held the week of June 12. In normal times, VLSI alternates between Hawaii and Japan. This year’s “location” is Japan.

The theme is “VLSI Systems for Lifestyle Transformation.”

The 2021 Circuits Symposium Chair, Ken Takeuchi, made these comments in his invitation:

“Even when Covid-19 is recovered in the future, our society may face the drastic lifestyle transformation. People may come to work in more remote manners and are less likely to physically move for both personal and business issues. The microscopic lifestyle change of individual people as well as macroscopic social structure change such as the company organization, city planning and transportation may occur. At the 2021 Symposium, considering these lifestyle transformations, we will discuss how state-of-the-art VLSIs can contribute to such lifestyle and heath transformations.”

The first technology symposium plenary hits directly at the pandemic with “Pandemic Challenges, Technology Answers” presented by Siyoung Choi, president and general manager of Foundry Business at Samsung. Although it has presented the industry with challenges, the pandemic has provided one of the biggest booms for the semiconductor business, and Samsung should have an interesting perspective on applying the lessons of the last year to its foundry business.

Between the nanosheets

With so few players involved at advanced nodes, one might think that there will be less diversity in the technology view. As we are down to two manufacturers currently at the most advanced 5 nm production nodes (Samsung and TSMC) there is some truth to that point.

On the other hand, however, technology change for the front end of the manufacturing flow is coming faster than ever as finFETS get set to retire. Two technologies are on the horizon as the industry needs to scale beyond the finFET.

The initial technology beyond the finFET will be the nanosheet transistor. This is broadly part of a concept that may also be described as gate all around or GAA. Nanowire is another term that readers may be familiar with which is only a slightly different flavor of nanosheet.

Nanosheet technology receives a full session (along with along with design technology co-optimization). in Session 15 and the plainly titled Nanosheet and DTCO.

IBM, Nvidia, Qualcomm, and Samsung are all represented on the technology co-optimization side, but the nanosheet papers in this session are all from academia.

The other papers on GAA technology are scattered around the conference. A couple are of particular note.

Jin Cai from TSMC will present CMOS Device Technology for the Next Decade as one of the modules of the first VLSI short course Advanced Process and Device Technology Toward 2nm-CMOS and Emerging Memory). Cai intends to discuss current finFET technology and give some roadmap view to the nanosheet device with TSMC’s vision. TSMC has held off for the next generation, instead extending finFET for the 3 nm node. Judging from a similarly titled presentation from IEDM 2019, the material may specifically include 2D material channel devices (more on this later).

The second module of the short course is from IMEC: Nanosheet Device Architectures to Enable CMOS Scaling in 3nm and Beyond: Nanosheet, Forksheet and CFET. This short course topic will be presented by IMEC’s director of Logic CMOS Device Technology Program, Naoto Horiguchi.

IMEC forksheet FETs (source: VLSI 2021)

With Samsung set to launch its MBCFET (multi-bridge channel FET) later this year, one should expect emphasis on this technology. (Yes, MBCFET is yet another term, the Samsung brand for nanosheet transistors.) Samsung is represented elsewhere in the conference, but does not have an entry for the MBCFET.

Its director for logic CMOS development introduced the topic as part of the gate all around roadmap in the short course, and IMEC reports the specific advancements in forksheet transistors in the second of the Technology papers sessions. Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space examines the integration of N- and P-channel devices to promote the area scaling advantages of the forksheet structure.

After the silicon and silicon-germanium nanosheet variants run out of steam, the industry will move to a fundamentally new class of channel materials.

2D or not 2D…

2D channel transistors will replace nanosheet devices in the next decade or so. Some landmark studies of these devices were examined in EE Times recently. As a more futuristic approach, this technology features more prominently at VLSI 2021.

There are five 2D materials papers accepted to this year’s conference, primarily in the third technology session – Future Logic Devices.

IMEC is well represented with two papers covering WS2 technology in the logic device session. The first is a device paper detailing gate scaling for dual gate WS2 transistors.

IMEC WS2 channel transistor (source: IEEE)

The second IMEC paper moves closer to the commercial feasibility of the 2D material concept by discussing process yield and uniformity for 300 mm wafers. The key point is the potential as integration of these transistors into backend of line process for monolithic 3D chips.

On that note, a research paper from Taiwan (National Yang Ming Chiao Tung University and TSRI) will present findings on monolithic 3D integrations for 2D materials. The abstract offers an opportunity to highlight some acronmyms that may pop up. Each time I am tempted to truncate “2D material channel transistor” to simply 2D or 2D transistor, I hesitate because this harkens back to pre-finFET days. Perhaps, I am just easily confused.

The NYCU-TSRI abstract offers us 2DM and M3D. These may not be the first appearances of the acronyms, but there is undeniable efficency in “M3D-2D electronics” as the authors describe future monolithic 3D integration of 2D materials channel transistors.

Popular 2DM’s for study offer attractive processing temperatures for integration with standard backend metal processing. It will be good to rememember those acronyms as the industry may be adopting these technologies in the next decade.

Although the logic session and the highlighted papers are interesting, another 2DM paper escaped this session to land on the rather blandly labeled Highlight or session 2. But this follows on the heels of the plenaries and is meant to capture the important papers for the conference.

Intel contributors will present Advancing Monolayer 2D NMOS and PMOS Transistor Integration From Growth to Van Der Waals Interface Engineering for Ultimate CMOS Scaling in the third slot of the session.

Intel presents the latest pathfinding results for 2D material transistors (source: VLSI 2021)

For those interested in the future of CMOS and the device roadmap several generations out, this paper is a must. Intel will compare progress on MoS2, WSe2, and WS2 along with the materials growth, gate oxide engineering, and contacts.

The GAA and 2DM papers are certainly forward-looking, but not nearly as futuristic as many to be found on the VLSI 2021 schedule. These transistor technologies are becoming well-established on the roadmap.

Get back to where you once belonged

Despite its focus on a very mature technology, there is a paper that caught my eye. With the eye-watering tool investments required for any semiconductor plant, squeezing extra generations out of old technologies has become a hallowed art in the business.

In that vein, Applied Materials and IBM authors examine the extendability of dual damascene copper below 28 nm metal line pitch. Dan Edelstein is in the author list. That name will be familiar to those with as much as peripheral interest in copper interconnect technology.

The AMAT/IBM researchers disclose two process flows for 10nm trace width metals. A new spin with selective deposition of tantalum-nitride-barrier along with reflowed copper (Cu/R-TaN/SB), is proposed for next generation mobile chips. For high performance computing applications, the research team suggests cobalt/copper composite.

10nm linewidth dual damascene metals from Applied Materials and IBM (source: VLSI 2021)

Flavors of these materials are currently in production, and their continued evolution and viability will be welcomed.

The wrap

Don’t take this limited preview as an indication of the breadth of deep technology topics to be presented at VSLI 2021. These are just a few high points that caught my attention, and those were only from the Technology Symposium. That track also offers memory and ferroelectric transistors and lots of other interesting papers to be digested with the time saved on the usual travel time to this conference (at least for Europeans and North Americans).

Many EE Times readers are likely more interested in the Circuit Symposium, but that must wait for another day.

Expo booth:

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Conference sessions:
  • Internet of Things (IoT)
  • Supply Chain
  • Automotive Electronics
  • Wave of Wireless
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