Optimizing Time to Bug / Questa Simulation Productivity – What’s New in Functional Verification from Mentor: Session 1

Mentor

Just like time and the tides, the complexity of electronic systems, and the need to verify that they will function correctly, wait for no one. Without a comprehensive suite of verification tools that evolves to fit the needs of this inexorable growth, it would quickly become impossible for you to do your job.

Please join us for a 5-part weekly web seminar series providing a comprehensive overview of Mentor’s Functional Verification tools and show how each tool has been optimized to find bugs as early in the verification process as possible. Each session will be presented twice at the times shown below consisting of two half-hour presentations.


Presenter

Tom Fitzpatrick-Strategic Verification Architect
Tom Fitzpatrick is a Strategic Verification Architect at Mentor, a Siemens Business where he works on developing advanced verification methodologies and educating users and partners on their adoption. He has been a significant contributor to several industry standards, both in Accellera and IEEE, including Verilog 1364, SystemVerilog 1800, UVM 1800.2 and is a founding member and current Vice Chair of the Portable Stimulus Working Group. He is also the 2019 recipient of the Accellera Technical Excellence Award. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification, Portable Stimulus and other functional verification topics and has produced some of the most popular and successful video training courses on Mentor’s Verification Academy website. Tom holds Master’s and Bachelor’s degrees in EE/CS from MIT, is an avid golfer and a huge Boston Red Sox and New England Patriots fan and has been married to his wife, Dee, for 24 years.

 


Gordon Allan-Questa Simulation Product Manager 
Gordon Allan is the Questa Simulation Product Manager at Mentor, a Siemens Business. Gordon was one of the developers of Accellera UVM, and was responsible for Mentor’s UVM/OVM Methodology Cookbooks published on the Verification Academy website and appreciated by over 65,000 engineers worldwide, as well as several conference papers on Verification topics at DVCon and elsewhere. Prior to joining the EDA industry in 2010 he gained over 18 years of SoC Design and Verification experience in lead engineer and senior consultant roles, working with many of the top semiconductor companies, fabless startups, system houses and EDA companies worldwide and giving him firsthand experience of customers’ challenges from spec to tapeout. Gordon is based in Silicon Valley.


Lucky draw

gift2
US$ 100 Amazon.com eGift card

Watch the webinar can enter the lucky draw. You may have a chance to win US$100 Amazon.com eGift card by random selection. 1 winners will be picked and announced after 3 months.


About Mentor Graphics Corporation
Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site: http://www.mentor.com.