Dynamic Flash memory, an alternative to DRAM, does not rely on capacitors. The result is a cell design with the potential for significant increases in transistor density.
Singapore-based DRAM specialist Unisantis Electronics revealed at this week’s (virtual) IEEE International Memory Workshop (IMW) advances in its work on dynamic flash memory (DFM) that it claims is a faster and denser technology than DRAM or other types of volatile memory.
The inventors of the technology, Koji Sakui and Nozomu Harada, claim a “leap forward” in the industry’s search for alternatives to DRAM for next-generation low-cost and high density embedded or standalone memory applications.
Unisantis was founded in 2008 by the inventor of flash technology, Fujio Masuoka, who patented surround gate transistor (SGT) technology, a 3D transistor design that offers significant system design and performance advantages to the manufacturers of memory and image sensor semiconductors and scales to very small nodes.
The presenters at the IMW noted that DRAM’s challenge has long been to continue packing in more storage for lower cost, without increasing power consumption. They suggest DFM takes a revolutionary approach to overcome limitations of conventional volatile memory such as DRAM, with its inherent short, regular and power-hungry refresh cycles, as well as destructive read processes.
DFM is also a type of volatile memory, but since it does not rely on capacitors it has fewer leak paths, it has no connection between switching transistors and a capacitor. The result is a cell design with the potential for significant increases in transistor density and —because it not only offers block refresh, but as a Flash memory it offers block erase — DFM reduces the frequency and the overhead of the refresh cycle and is capable of delivering significant improvements in speed and power compared to DRAM.
Using TCAD simulation, researchers at Unisantis have proven that DFM has a substantial potential to increase density 4X compared to DRAM. The scaling of DRAM has almost stopped at 16Gb, according to recent IEEE ISSCC (International Solid-State Circuits Conference) papers.
Modelling DFM at 4F2 cell density shows how perfectly structured DFM is (see diagram below).
The design and development of DFM means significant Gb/mm2 improvements, and today’s limits on DRAM (currently 16Gb) could immediately see increases to 64Gb memory using DFM’s radically enhanced cell structure.
Replacing DRAM is a major challenge for the industry, not only because, as recent forecasts from market research group Yole Development have suggested , DRAM today accounts for over 50% of the current market demand for memory
Forecasts also suggest the need for this type of low cost, high density DRAM by 2025 will continue to grow and exceed $100Bn. But technology challenges also lie ahead presented by some of the proposed replacements, including capacitor-less DRAM, ZRAM or simplistic GAA and Nanosheet approaches, all which have their own limitations compared to DFM.
Unisantis developed DFM with the proven technological principles of its patented SGT Technology building on that work and the company’s innovations, particularly in memory semiconductors.
Commenting on the breakthrough, Sakui said: “The memory industry has long since accepted DRAM technology is nearing the end of its life, but its significant market means any replacement technologies must provide the right balance of performance, costs and future scalability.”
Unisantis says the company will now focus on further development and, in parallel, testing and demonstrating the features the full and full potential of DFM externally to convince the industry that its technology is the leading long-term viable option to DRM.
It said it is in discussions with several memory makers and foundries on partnerships, but would not elaborate.
This article was originally published on EE Times.
John Walko is a technology writer and editor who has been covering the electronics industry since the early 1980s. He started tracking the sector while working on one of the UK’s oldest weekly technology titles, The Engineer, then moved to CMP’s flagship UK weekly, Electronics Times, in a variety of roles including news deputy and finally editor in chief. He then joined the online world when CMP started the EDTN Network, where he edited the daily electronics feed and was founding editor of commsdesign.com (which, over the years, has become the Wireless and Networking Designline). He was editor of EE Times Europe at its launch and subsequently held various positions on EE Times, in the latter years, covering the growing wireless and mobile sectors.