Understanding Voltage Derating and Dynamic RDS(ON) for eGaN FETs in Synchronous Rectification Applications

Article By : Andrea Gorgerino, EPC Corp.

As GaN devices gain wider adoption in the market, the drain-to-source voltage derating criteria is often one of the first decisions designers make for selection of a proper power switch.

As gallium nitride (GaN) devices gain wider adoption in the market, the drain-to-source voltage derating criteria is often one of the first decisions designers make for selection of a proper power switch. This topic is tightly related to what happens when a device is used beyond its maximum rating.

Silicon (Si) MOSFETs typically have an avalanche rating allowing them to operate beyond their maximum drain to source rating: the device will clamp the overvoltage at the avalanche voltage dissipating the excess energy. This event can be quite stressful and compromise long term reliability. However, EPC eGaN FETs behave very differently: they do not have an avalanche effect and, therefore, no avalanche rating; but instead are rated to operate up to 120% of their maximum drain-to-source voltage for transient events. This operation condition has been very well characterized and modeled, resulting in a good understanding of what happens to accurately predict the impact on lifetime.

The main concern for GaN transistors operating beyond the maximum drain to source rating is dynamic on-resistance. This is a condition whereby the on-resistance of a transistor increases when the device is exposed to high drain-source voltage (VDS). The traditional test for this condition is to apply maximum-rated DC VDS at maximum-rated temperature (typically 150°C). If no failures occur after a certain amount of time —usually 1,000h—the product is considered good.

EPC has developed a first principle physics-based model to explain RDS(on) rise in GaN transistors under hard-switching conditions. The model is predicated on the assumption that hot electrons inject over a surface potential into the conduction band of the surface dielectric. Once inside, the electrons quickly fall into deep mid-gap states, where they are assumed to be trapped permanently (no de-trapping). Hot electrons are created during the switching transition, where the transient combination of high injection current and high fields leads to a hot carrier energy distribution with long tails into the high energy regime.

This model predicts the following observations:

  • RDS(on) growth with time
  • The slope of RDS(on) over time has a negative temperature coefficient (i.e. lower slope as temperature rises)
  • Switching frequency does not affect the slope but causes a small vertical offset
  • Switching current does not affect the slope

Having understood the underlying degradation mechanisms and effects, these models can be applied to real applications. The following demonstrates two synchronous rectification application examples and the lifetime impact from typical switching waveforms calculated: a synchronous rectifier output stage and a synchronous buck converter.

A realistic SPICE model was developed for the application circuits based on EPC’s reference designs, including the effects of parasitic layout inductances. These parasitic inductances are the main contributors to ringing and voltage over-shoot which can impact dynamic RDS(ON) in the GaN device itself. The value of these parasitic inductances was increased to mimic the effects of poor PCB layout. The SPICE simulations captured channel current and drain to source voltage during one switching period, at steady state.

The next step was to apply these single-cycle current-voltage loci into the hot electron trapping model (implemented in MATLAB). This model calculates the charge trapping that occurs in each switching cycle, and determines at what times (e.g. turn-on or turn-off transitions) the most charging occurs. Integrating this model over the 10 year projected continuous operation of the application with identical switching cycles allows us to determine the cumulative charge trapping that occurs. Because the instantaneous trapping rate depends (non-linearly) on the cumulative trapped charge, the amount of charging per cycle is not constant, but instead rapidly self-quenches over time as the FET switches. Not only does the charging saturate in time, but the regions within a switching waveform that are most detrimental can also change as the device operates. This is automatically taken care of during integration of the model.

For the first example, an output stage of 48V – 12V LLC converter was chosen – commonly used in server and artificial intelligence applications. Again, a SPICE model was developed to include the main layout parasitic inductances as shown in Figure 1 based on the EPC9149 demonstrator. By changing L1…L4 it was possible to change the overshoot seen by the output stage devices as shown in Figure 2.

Figure 1 Spice model for LLC converter 48V – 12V operating at 1MHz.

Figure 2 Low and high overshoot cases for LLC converter.

The calculations of voltage, current, and dRDS(on) for the entire sequence of switching waveforms from the first cycle to the 10 millionth cycle were made. Throughout each cycle, the amount of trapped charge QS was calculated and summed with all previous cycles.

This calculation was performed assuming the use of 40V devices, there is no increase in RDS(ON) over the 10year lifetime of the application for both low and high overshoot cases.

The exercise was repeated assuming the use of 30V devices, again there is no increase in RDS(ON) during the 10 year lifetime of the application for both low and high overshoot cases.

Users can consider using 30V eGaN FETs instead of 40V devices in this application without worry over dynamic RDS(ON) increase because of the voltage overshoots, thereby taking advantage of the 30V devices lower RDS(ON).

For the second example, a synchronous FET of a 48V – 12V buck converter was looked at operating in continuous conduction mode at 500kHz. As shown in 3 a SPICE model was developed based on the EPC9078 demonstrator.

Figure 3 48V-12V synchronous buck converter operating at 500kHz.

Figure 4 Low and high overshoot case for sync buck converter.

By varying L5 it is possible to vary the overshoot seen by the devices: the two conditions analyzed for the low side synchronous eGaN FETs are with overvoltage of 50V and 90V (170V peak) as seen in Figure 4. This second value is well beyond normal application conditions.

The results, assuming the use of a 100V eGaN FET, is minimal RDS(ON) increase with 50V overshoot, while there is a more significant degradation when the device sees 170V peak voltage.

These two examples illustrate that it is possible to clearly quantify the effects of dynamic RDS(ON) depending on actual use conditions. The results are very positive showing the robustness if EPC eGAN FETs. Users now have a tool to determine the derating needed in their applications and can take full advantage of these devices by reducing voltage derating factors.


About the Author

Andrea Gorgerino is the Director of Global Field Application Engineering at EPC Corp.


EPC is the leader in enhancement mode gallium nitride (eGaN) based power management. eGaN FETs and integrated circuits provide performance many times greater than the best silicon power MOSFETs in applications such as DC-DC converters, remote sensing technology (lidar), motor drives for eMobility, robotics, and drones, and low-cost satellites. Visit our web site: www.epc-co.com.tw. Follow EPC on social media: LinkedIn, YouTube, Facebook, Twitter, Instagram, YouKu. eGaN is a registered trademark of Efficient Power Conversion Corporation, Inc. For more information, please contact Winnie Wong (winnie.wong@epc-co.com).


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