TSMC’s Japan Expansion Puts Profit at Risk

Article By : Alan Patterson

Operating costs are expected to rise as the foundry giant shifts production overseas.

Last week’s announcement by Taiwan Semiconductor Manufacturing Co. (TSMC) that it plans to build its first chip facility in Japan is yet another sign that the world’s biggest semiconductor foundry will face higher costs as it moves more of its production outside of Taiwan.

TSMC’s plan is subject to board approval later this year.

Western nations are demanding a secure supply of semiconductors as their domestic automakers continue to idle production lines because of chip shortages. Those governments are seeking manufacturing investments from leading chip makers in Asia such as Samsung of South Korea and TSMC of Taiwan, as well as Intel.

As Samsung and TSMC shift production out of highly-integrated domestic ecosystems to locations where the supporting infrastructure is less complete, costs will inevitably rise, according to Matt Bryson, senior vice president of equity research at Wedbush Securities.

“Overseas fabs will almost certainly be less profitable on a margin basis versus current business,” Bryson said in an email. “Take the new [TSMC] Japan fab for instance. Even assuming 50 percent of the fab is paid for by Japan, there is still depreciation.”

That new Japanese fab will compete with much older 28-nm operations that are fully depreciated, Bryson noted. Add to that potentially more cost burdens for TSMC. “Will TSMC receive the same favorable utilities pricing they presumably get in Taiwan?” Bryson noted.

TSMC’s new fab will receive subsidies from Japan. “We have received a strong commitment to support this project from both our customers and the Japanese government,” TSMC CEO C.C. Wei told investors last week. He didn’t disclose details on what support the Japanese government will provide.

The fab will make wafers at the 28- and 22-nm process nodes, with first production targeted for May 2024. The planned investment in Japan came so quickly that it is not included in the $100 billion that TSMC earlier this year said it plans to spend for capacity expansion in the next three years.

In the U.S., where TSMC is building a new chip facility in Arizona, the cost structure will also be higher than in Taiwan. While most of TSMC’s production is in Taiwan, the company operates a 12-inch “gigafab” as well as an older 8-inch facility in China along with an older 8-inch facility in the U.S.

Early in 2020, TSMC announced it would build a fab to make chips at the 5-nm process node in Arizona with financial support from that state and the U.S. government. The agreement between TSMC and the U.S. came as the semiconductor industry was caught in the middle of a geopolitical competition between the U.S. and China to dominate new technologies such as 5G and AI, both of which are growth drivers for the Taiwanese company.

TSMC Chairman Mark Liu said in a recent interview with Time Magazine that costs in the U.S. are “much higher” than TSMC expected. In spite of the higher costs, more governments may ink similar pacts with TSMC.

“We don’t rule out the possibility of building a fab in other areas that include Europe,” CEO Wei told analysts at last week’s meeting.

Higher costs

In July, TSMC said that it aimed to “firm up” wafer prices. Now, the company is talking more about raising prices for customers ranging from Apple to Xilinx.

Pricing is “a very private discussion between TSMC and our customers”, Wei said.

“Wafer prices should lift into next year,” said Bryson. “I think the press reports of 10 percent to 20 percent are accurate, but the implementation of price increases will certainly depend on terms [and] timing of current agreements with each customer.”

The company reiterated its wafer pricing strategy is “strategic, not opportunistic,” and aimed at anticipating future waves of capacity expansion that grow increasingly expensive.

For now, TSMC has boosted its outlook for profit margins to greater than the 50-percent range it has typically posted.

The company’s higher margin guidance is strong evidence that customers are willing to pay more, according to Sebastian Hou, senior investment analyst at Neuberger Berman. More customers are making what TSMC calls “pre-payments” to help secure chip supplies, Hou said.

Previously, only a few customers entered such agreements. But in order to meet strong demand and secure customer commitments, TSMC said that more customers are joining the pre-payment system.

Meantime, manufacturing costs are increasing at the leading nodes such as TSMC’s upcoming “N3” or 3-nm process technology.

Costs will be higher than at the existing N5 node, according to Wei.

“That is because of technical complexity, and we have to use many new pieces of equipment for which the cost is higher.”

TSMC has so far been able to pass on higher prices to its customers.

“We expect TSMC to have a lift from higher pricing, plus rising average sales prices from node migration and structural drivers, allowing for outperformance even as cyclical worries continue,” Randy Abrams, Credit Suisse managing director, said in an Oct. 15 research report.

This article was originally published on EE Times.

Alan Patterson has worked as an electronics journalist in Asia for most of his career. In addition to EE Times, he has been a reporter and an editor for Bloomberg News and Dow Jones Newswires. He has lived for more than 30 years in Hong Kong and Taipei and has covered tech companies in the greater China region during that time.

 

Subscribe to Newsletter

Leave a comment