TSMC introduced its N4 process node, and provided details on its subsequent N3 process.
Even as it ramps up production on its N5 process, Taiwan Semiconductor Manufacturing Co. (TSMC), at its annual Technology Symposium, introduced its N4 process, which it said is scheduled to come online in late 2021, with volume production in 2022. Anticipating the inevitable question, the company also provided some details about its subsequent N3.
Before getting into the intermediate future, TSMC offered some near-future news. The company revealed a plan to implement an enhanced version of N5, called N5P, in 2021. The N5 refinement will provide an additional 5 percent speed gain and 10 percent power improvement over N5, TSMC said.
N4, the company promised at its annual Technology Symposium, will be a “straightforward migration” from, and an extension of, N5, of course with some performance, power and density enhancements. On the production side, TSMC said it will be able to reduce the number of mask layers somewhat. On the design side, the company said it will have design rules, SPICE and IP compatible with N5.
N4 will be a more-or-less incremental advance; the big process-node leap will be the N3 — TSMC called it a “generational leap.” Compared to the original version of N5 (yes, the N5), the N3 will offer about 1.7 times the logic density (similar to the 1.8X jump from N7 to N5), an improvement in speed of 10- to 15 percent at the same power, and conversely a power reduction of 25- to 30 percent at the same speed.
Somewhat surprisingly, TSMC is planning to ride finFET technology down into the N3 process generation. As one of the analysts listening in to the virtual conference noted during the Q&A, finFET technology has been offering diminishing returns from one process generation to the next. TSMC said it has consulted with its customers, who are apparently comfortable with the promised performance improvements. That includes customers in both the mobile and high performance computing (HPC) markets.
The company is shooting for initial runs in 2021, but doesn’t expect to ramp to full production volumes in N3 until the latter half of 2022.
The company also touted its N12e, a refinement of its ultra-lower power technology optimized for edge AI devices. TSMC claimed N12e, a variant of the company’s 12FFC+ technology, is the first ultra-low power technology to use FinFET transistors.
TSMC kept hammering the point that it has the best process technology in the world. That was a boast Intel used to be able to make, but no longer. Still, Intel has recently been making the argument (which many find compelling) that architectural innovations have become equally important, packaging is critical, and that system-level expertise counts.
TSMC studiously avoided mentioning any competitors, including Intel, but made it clear that it can compete on architecture and innovation.
On the packaging side, TSMC has 3DFabric, its umbrella term for both its Silicon Stacking and Advanced Packaging Technologies. The techniques allow, for example, the integration of DRAM with SoCs, which the company noted reduces the size of the mainboard and allows for further integration of RF and sensor technologies.
TSMC also emphasized its “specialty technologies,” including MEMS, image sensors, embedded memory, RF, analog, high voltage, and power ICs, which “combine seamlessly with TSMC’s advanced logic technology to provide optimal system-level solutions for our customers.”
The company also asserted it has made “some major breakthroughs in new materials and architectures, such as high mobility channel, nanosheet/nanowire, 2D materials, carbon nanotube, and more.”
The topline concern of just about everybody in the electronics industry is topline performance at an acceptable price, but TSMC lays claim to running the most efficient fabs on Earth. Just because going green has cost benefits, that’s no reason to get unduly cynical.
The company’s specific goals for its process technology, including trying to decrease:
Long term, the company said it is commited to several ambitious goals, including: