TSMC's 3nm technology, starting production later in 2022, will feature the company's FinFlex architecture offering choices of standard cells with a 3-2 fin configuration for performance, a 2-1 fin configuration for power efficiency and transistor density, or 2-2 fin configuration for efficient performance.
Taiwan Semiconductor Manufacturing Co. (TSMC) has created versions of its upcoming 3nm FinFET node that’s ramping up later this year, allowing chip designers to enhance performance, power efficiency, and transistor density — or select a balance of those options.
TSMC’s 3nm technology, starting production later in 2022, will feature the company’s FinFlex architecture offering choices of standard cells with a 3–2 fin configuration for performance, a 2–1 fin configuration for power efficiency and transistor density, or a 2–2 fin configuration for efficient performance.
The world’s leading chip foundry announced FinFlex at its 2022 North America Technology Symposium last week. With the new architecture, customers can create SoC designs with functional blocks implementing various fin configurations to meet performance, power, and die–size targets.
“Demand for computational power and energy efficiency is growing faster than ever before, creating unprecedented opportunities and challenges for the semiconductor industry,” TSMC CEO C.C. Wei said at the event.
By offering a range of choices when the new 3nm node starts up, the company will plug gaps that rivals like Samsung or Intel may seek to exploit as the three companies aim for process technology leadership. TSMC has captured 90% of the business in the advanced 7nm and 5nm nodes, according to market research firm Gartner.
TSMC said its 3nm process technology was designed to enable the combination of fin configurations.
“Working closely with our EDA partners, we will enable our customers to take full advantage of TSMC FinFlex in their products by using the same toolset,” said Godfrey Cheng, global marketing head at TSMC.
One recent trend for chip designers is the hybrid CPU, according to Cheng. The new CPUs feature cores for high–performance as well as others for power efficiency along with GPU cores and fixed function blocks. The power efficient CPU cores handle most of the everyday workloads. As the workloads increase, the high–performance cores activate. Complementing these CPU cores are ultra–efficient and ultra–dense GPU and fixed function blocks.
With TSMC FinFlex, product designers can optimize fin configurations for each of these functional blocks without affecting others, all on the same die, according to Cheng.
At last week’s technology symposium, TSMC also announced it is developing N6e, a process technology designed to provide improved computing power and energy efficiency for edge AI and IoT devices. N6e will be based on TSMC’s 7nm process.
As leading foundries adopt heterogeneous integration at advanced nodes, packaging technology has seen increased importance.
At the symposium, the company presented its SoIC chip–stacking technology, including the world’s first SoIC–based CPU employing chip–on–wafer (CoW) technology to stack SRAM as a Level 3 cache.
The company also gave details on an intelligence processing unit stacked on top of a deep trench capacitor die using wafer–on–wafer (WoW) technology.
With 7nm chips in production for both CoW and WoW, TSMC said it will offer the packaging technologies for 5nm starting in 2023. To meet demand for SoIC and other TSMC 3DFabric system–integration services, the company will start production from the world’s first fully automated 3DFabric factory in the second half of 2022.
This article was originally published on EE Times.
Alan Patterson has worked as an electronics journalist in Asia for most of his career. In addition to EE Times, he has been a reporter and an editor for Bloomberg News and Dow Jones Newswires. He has lived for more than 30 years in Hong Kong and Taipei and has covered tech companies in the greater China region during that time.