TSMC Adds a N5P process

Article By : Rick Merritt

The Taiwan foundry sketched out a laundry list of processes and packaging options including a new N5P node at an annual event.

SANTA CLARA, Calif. – TSMC added a N5P process and more details on advanced packages to its road map for squeezing advances from silicon at an annual event here.

At the bleeding edge, picking a path forward among expanding 7, 7+, 6, 5 and 5+ options is increasingly complex. “The good news is we continue to see scaling for the foreseeable future,” Yuh-Jier Mii, a senor vice president for technology development for TSMC told an audience of about 2,000 attendees.

Even chief executive C.C. Wei cracked a joke over TSMC’s news last week of a 6nm option that will start risk production a year after its previously announced 5nm node. “I had to ask my R&D people what was their thinking – was that for fun? Next time you won’t be surprised if I release an N5.5,” he quipped in a keynote.

TSMC’s N5 process started risk production in March and will offer 80% more density and 15% more speed or 30% less power than its N7 node now in volume production. Using new eLVT transistors, speed gains could hit 25%.

The N5P starting risk production next year could squeeze anther 7% in speed or 15% in power from N5 using the same design rules. The gains come in part from enhancements to a fully strained high-mobility channel.

TSMC showed an N5 wafer with SRAM yields above 90% and logic yields above 80% from the first phase of its new Fab 18. Shells for two more phases are under construction. A few key IP blocks for N5 such as PAM4 serdes and HBM blocks are still in development.

N6 lacks the performance and power boosts of N5 but will offer an 18% shrink over N7 (8% over N7+) and uses existing N7 design rules and blocks. However, N6 won’t start risk production until Q1 2020 and a key design library for M0 routing is still in development.

Last week, rival Samsung announced it had taped out a chip in what it described as a custom 6nm process. The timing of TSMC’s move left one analyst scratching his head.

“The only answer I can come up with is they expect customers to be slow to move to 5nm, so they’re offering 6nm as a cost saver. Presumably, the die shrink offsets the cost of a new mask set,” said Mike Demler of the Linley Group.

TSMC is using extreme ultraviolet lithography on “a few critical layers” for N7+, the foundry’s first EUV process starting volume production in Q3 2019. N6 uses one additional EUV layer and N5 adds “more layers.” Designers should see about a 10% mask decrease due to EUV at N7+ and additional reductions at N6 and N5.

The latest EUV machines support a stable 280W light source that TSMC expects to hit 300W by the end of the year and greater than 350W in 2020. Uptime increased from 70% last year to about 85% today and should hit 90% next year. EUV “exceeded our needs,” said Mii.

Not everyone was captivated by the additional options. Another analyst advised designers to skip the interim nodes from both TSMC and Samsung. “Customers should focus on 5nm and 3nm and ignore some of the other options, such as 6nm and 4nm within the multiple-choice arena,” said Handel Jones, president of International Business Strategies.

Jones also cautioned designers to wait until a foundry has produced 100,000 wafers on a new node to avoid early bugs given the costs of developing and qualifying new IP blocks (see below).

Node Costs IBS

Estimated rise in costs for work at advanced nodes. (Source: International Business Strategies, Inc.)

Toward 3nm, advanced packaging and specialty modules

TSMC reported on research paving a path to 3nm and 2nm nodes, but stopped short of describing new transistors they will require. Sulfide and selenide 2D materials promise good mobility as channel thickness drops below 1nm and can deliver higher drive current than silicon at 7nm gate lengths, Mii said.

The foundry developed a new low-k film more resistant to depletion effects as chip dimensions shrink. It also showed regular metal lines made at 30nm using a new reactive ion etch process.

In more mainstream nodes, it said its 22ULL node will support 0.6-0.9 voltages for battery-operated chips. HDMI blocks are still being developed and USB, MIPI and LPDDR blocks are still being qualified for the process that is an upgrade of its 28nm node.

In packaging, TSMC provided new details on its latest options—SoIC and Wafer-on-Wafer. WoW only works with two die of the same size while SoIC can stack multiple die of different sizes. Both target mobile and high-performance computing systems but are still in development with commercial products not expected until 2021.

Both options are front-end processes that bond die directly using copper pads with interconnect pitches starting at 9 microns. Through silicon vias (TSVs) make connections to external micro-bumps.

By Q3, TSMC will provide macros as a starting point for TSV designs. Thermal models will follow by the end of the year.

Node Choices IBS2

The menu of process nodes available or in the works. (Source: International Business Strategies, Inc.)

Meanwhile, the foundry is extending its 2.5D CoWoS process this year to support devices twice the reticle size. Next year it will expand to 3x the reticle size and support for five metal layers with deep trench capacitors in the silicon substrate to ease signal and power integrity challenges.

TSMC also reported advances across about seven different specialty processes it offers for embedded memory, image sensors, MEMS, and other components. Increasingly it aims to package them as modules closely tied to logic nodes.

In RFSOI, it is moving 180nm capabilities on 200mm wafers to a 40nm node on 300mm wafers. For 5G phones it is optimizing 28/22nm nodes for millimeter wave front-end modules and its 16FFC node for mmwave and sub-6GHz transceivers.

For microcontrollers, embedded MRAM started risk production in a 22nm node last year and resistive RAM will start risk production in the node later this year. “The emerging memories have final emerged,” said Kevin Zhang, a TSMC business development manager.

This year, TSMC aims to spend about $10.5 billion on capex, increasing its capacity just 2% to about 12 million 12-inch wafers/year. About a million of those wafers will be at leading edge 10nm and 7nm nodes, said J.K. Wang who oversees TSMC’s fab operations.

“It was a solid roadmap update for TSMC…it’s interesting that both TSMC and Samsung have EUV up and running ahead of Intel,” said Kevin Krewell, analyst with Tirias Research.

Subscribe to Newsletter

Leave a comment