TII process reduces chip fabrication time

Article By : Rick Merritt

The TII approach can cut 50% off the costs of the widely used SADP technique used at 16nm while improving throughput by as much as 35%.

Berkeley researchers have described a technique that they say cuts the cost and time of making chips while creating features smaller than today’s most advanced processes. The so-called tilted ion implantation (TII) process created features as small as 9nm.

The lab work shows promise for reducing the rapidly increasing cost and complexity of making chips, which has slowed progress in Moore’s law. However, it’s unclear whether chip makers will adopt the technique.

“We are using argon ions to selectively damage certain parts of the silicon dioxide layer,” said Peng Zheng, lead author of a paper published in the latest issue of the IEEE Transactions on Electron Devices. “It’s self-aligned, tilting down with pre-existing mask features, so it doesn’t have the issues of [the existing] LELE [method], where misalignment is a killer.”

The approach could cut 50% off the costs of the widely used self-align double patterning (SADP) technique used today at 16nm and beyond while improving throughput by as much as 35%, he said.

“Implantation is very cheap… compared to SADP, with its multiple layer deposition and cleaning process,” he said, noting that SADP also requires relatively expensive materials that can withstand processing at 150°C.

The 9nm feature size in the paper suggests that TII could be used to create 18 to 20nm pitches. By contrast, TSMC said that its smallest pitches to date are 40nm for an M0 layer in its 7nm process described in a paper at the recent IEDM event.

The technique was first described in 2015 to two of the paper’s supporters, Applied Materials and Lam Research. The results of the lab demo were presented in a lithography conference last year.

Will companies make the switch?

Given that TII uses “fairly standard CMOS processes … I’m pretty sure some fabs have tried it—this is very easy compared to SADP—but they won’t say anything until they put it in high-volume manufacturing because this industry is so competitive,” Zheng said.

Any adopters would have to license the patent-pending technique through the Berkeley technology transfer office, he added.

As a follow-on, researchers are exploring how to use the technique to pattern tiny holes. They also are exploring how it could be used to help relax the tight design rules currently required using SADP at 16nm nodes and beyond. In addition, they continue to experiment with new materials.

The paper had two noteworthy co-authors—Leonard Rubin, the chief device scientist at Axcelis, and Tsu-Jae King Liu, a Berkeley vice provost and co-inventor of both the FinFET and SADP. For his part, Peng Zheng recently graduated from Berkeley with his PhD and accepted a job in advanced process development at Intel.

“It’s definitely impressive work,” said G. Dan Hutcheson, chief executive of market watcher VLSI Research.

However, Hutcheson noted several business issues that could stand in the way of adopting the technique.

“Cost improvement, while impressive on paper, is seldom enough to get companies to switch—just look at SOI,” said Hutcheson, pointing to the long road to market that silicon-on-insulator has travelled.

“There are lots of unanswered risk questions, like yield and damage to underlying layers,” he said, adding that chip makers are “typically very conservative when it comes to implant.”

First published by EE Times U.S.

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