The Need for Faster Time to Insight Opens the Door for New Testing Category

Article By : Michael Seaholm, Tektronix

Engineers today need tools that complement the performance of existing equipment by providing faster time to insight, superior ease-of-use, while not significantly impacting capital budgets for their projects.

Less than 20 years since the PCIe 1.0 specification was introduced by the PCI Special Interest Group, the industry is already preparing for PCIe Gen 6.0. With each new generation of the standard doubling the data rate of the previous generation, PCIe Gen 6.0 is more than 25 times faster than the original PCIe Gen 1.0 specification introduced in 2003.

This doubling of data rates every three years has introduced countless challenges for validation engineers responsible for the physical layer performance of their PHYs, chips, cards, and systems – not all of which are being fully addressed by testing equipment available today.

While the majority of these challenges have been addressed by the increasing performance of key electrical validation equipment like oscilloscopes and bit error rate testers (BERTs), these performance improvements have also impacted testing complexities in setup and equipment usage, which has contributed to increased testing and debug times for validation teams. It is a natural progression that test equipment performance exceeds that of the standard it sets out to validate, but some of the challenges engineers face are not being fully addressed with test equipment performance improvements alone.

Engineers today need tools that complement the performance of existing equipment by providing faster time to insight, superior ease-of-use, while not significantly impacting capital budgets for their projects. A case for each of these needs can be made by looking at industry macrotrends.

Time-to-Market Challenges: The Case for Faster Time to Insights in PCIe Testing

Because the latest PCIe standards must support all previous PCIe generations, the testing matrix for each new PCIe generation grows exponentially for validation teams. This, coupled with the increasing testing complexities as the standards progress, has significantly increased overall testing times for programs working to implement the latest PCIe standards. What further complicates the situation is the expectation that these teams produce next generation products in a similar time-to-market window as previous generations.

Evaluating link performance and debugging problems takes longer than ever, and the equipment available today does not support engineers in a way that saves them the days or weeks of debug and performance evaluation necessary to support these timelines. There will always be a need for high-performance tools like oscilloscopes and BERTs that focus on pushing performance boundaries, but the industry needs a new tool in the tool bag. The modern engineer needs a new category of test and measurement equipment that is easier to set up and use, and that delivers faster time-to-insight to allow for more frequent testing during design and validation to identify issues earlier in the development cycle.

Expected Labor Gap: The Case for Ease-of-Use in PCIe Testing

As the digital world becomes more deeply ingrained in everyday life, the demand for semiconductors and semiconductor devices continues to grow exponentially. This parabolic growth has most notably led to significant challenges for the industry in terms of supply chain and logistics. What is less-often discussed, and what may be most concerning, is the expected shortfall in the engineering workforce to support the growth. According to a presentation from the 2022 SemiCon West conference, by 2030 there is an expected deficit of approximately 300,000 engineers needed to support the growth of the semiconductor industry. This deficit is largely attributed to fewer new college graduates transitioning into the industry, and the expected attrition from the industry, over the coming years.

This expected labor shortage serves to be a significant complication for companies in the industry, and one that is not easily solved due to the technical nature of development and validation of HSIO (High Speed I/O) devices. PCIe in particular is positioned to grow increasingly complex as successive generations of the standards are released. The workforce gap to support development and validation of these devices is expected to put further stress on program timelines and testing workflows for engineering teams across the industry.

In order to address this expected labor gap across the industry, companies may be required to assign engineering tasks more broadly than in the past, creating a need for testing equipment that is easier to set up and operate than existing solutions. As this macrotrend unfolds, it will become increasingly important to have equipment that requires less training and expertise to operate, yet still provides meaningful insights into the health and performance of HSIO devices.

Monetary Scrutiny: The Case for Capital Budget Optimization in PCIe Testing

As data rates have increased for subsequent standards of PCIe, so has the need for higher-performance equipment. The bandwidth requirements needed to support this equipment continues to grow, and with that performance comes significant cost for acquiring full testing suites. These costs are so significant that even larger companies are often in a position to purchase only a few complete systems. Smaller companies see an even greater impact, as they often cannot afford the equipment needed for complete validation testing, and instead must rent or use third-party testing facilities to conduct their validation and debug.

Because performance is paramount for full PCIe evaluation and compliance testing, companies have to undertake significant equipment costs to perform testing, whether they choose to purchase or rent. While there is no way to avoid this entirely, equipment that can provide meaningful insights into designs earlier and faster, without putting significant strain on capital budgets for programs, will increasingly become a welcome solution. Having equipment that can accelerate testing by increasing the number of test setups and reducing overall testing times, without putting significant strain on program budgets, prepares engineering teams to efficiently use the higher-performance equipment when it is needed.

Answering the Call: A New PCIe Test and Measurement Solution is Now Available

There will always be a need for high-performance validation and compliance testing equipment, but equipment that can accelerate time-to-insights, is easy to use, and cost-effective, is a vital complementary solution to the existing tools in the testing workflow for PCIe today.

Figure 1: Eye diagrams are presented to the user by the TMT4 Margin Tester in real time.

Tektronix is dedicated to understanding the needs of the industry by evaluating macrotrends and speaking with customers to develop breakthrough innovation that solves real-world problems. The latest innovation from Tektronix, the TMT4 Margin Tester, is the first and only solution on the market with a focus on speed and ease-of-use for PCIe Gen 3 and Gen 4 testing, while also considering the capital budget constraints of the industry.

Figure 2: TMT4 Margin Tester

The TMT4 Margin Tester is the latest example of Tektronix developing a breakthrough product as the result of deeply understanding industry and customer needs.

Tektronix is committed to re-imagining the world of test and measurement, addressing customer pain points, and improving workflows for customers as the world evolves.


About the Author

Michael Seaholm is Product Manager, Performance Oscilloscopes, at Tektronix.

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