DRAM creates new possibilities for designers, with DDR5 featuring bandwidth and efficiency improvements to enable AI, high performance computing, niche applications...
The latest iteration of double data rate (DDR) DRAM offers many advances over its predecessor, and also creates new possibilities for designers building memory devices, and perhaps even the odd challenge.
The JESD79-5 DDR5 SDRAM standard, published by the JEDEC Solid State Technology Association earlier this year, was designed to meet increasing needs for efficient performance in a wide range of applications including client systems and high-performance servers. The latter segment is facing increasingly more performance pressures from intensive cloud and enterprise data center applications. Overall, the DDR5 specification provides developers with twice the performance and much improved power efficiency in comparison to DDR4.
More specifically, the DDR5 standard is architected to improve scaling performance without degrading channel efficiency at higher speeds, which has been achieved by doubling the burst length to BL16 and bank-count to 32 from 16. JEDEC describes the DDR5 architecture as “revolutionary,” in that it provides better channel efficiency and higher application-level performance that will enable the continued evolution of next-generation computing systems. For increased reliability and efficiency, a DDR5 DIMM boasts two 40-bit fully independent sub-channels on the same module.
Despite the significant leaps forward from DDR4, DDR5 doesn’t mean a radical change for designers, said Jim Handy, principal analyst with Objective Analysis. “Since the first DDR, reference designs have been used for all board layouts, and every part of the memory subsystem has to go through validation.” That includes everything from connectors to DIMMs. “By the time it gets to the design engineer it will all be proven out, so there’s really no difference between DDR4 and DDR5 from a design perspective.”
Not many designers need to choose between the two either, he added. “That decision was made by the processor manufacturer.” One processor may require the use of DDR4, while the other may require DDR5. Other than processor architects, the only people in position to choose are those who design their own FPGAs and ASICs. “Not very many of those designs use DRAM.”
Handy said the most notable aspect of DDR5 is that it’s even faster than DDR4, “which was already awfully fast.”
DRAM maker Micron Technology sees few challenges with the move to DDR5, said Micron Lead Architect Frank Ross, although moving voltage regulation from the system to the DIMM will take some getting used to. “There’s great advantages for us having that on the DIMM and simplifying the motherboard and improving the power delivery network.”
The challenges posed by differences between DDR4 and DDR5 aren’t steep ones, he said. “Every time we go to these kinds of faster speeds, especially the speeds that we’re looking at for DDR5, there’ll be some new challenges for making sure the signaling is good, and that comes from both the system design and motherboard design side.” There will be a lot of new training algorithms that will need to be developed, said Ross. “That’ll be an adjustment for everybody.”
The training required is a reminder that there’s a lot involved in simply doubling the speed of DRAM from one iteration to the next, he said, but that all the work to enable the improvements of DDR5 have been with the intent to make sure the specification has a long run well into the future, and that’s why reliability is critical. Densities are beginning at 16Gb and eventually 32Gb, with an interim step of 24 likely, said Ross. “The big deal for us since this was going to last for a long time was making sure that we were going to be addressing the DRAM scaling going forward, so we really had to look very closely at reliability.”
From a use-case scenario, reliability is critical as a great deal of DRAM demand is coming from data centers that support enterprise-class private and public clouds, which continue to grow at a rapid pace and where initial update of DDR5 is expected. “We have to make sure we’re providing the kind of reliability that’s going to operate at scale.” Ross said doubling the bandwidth is only part of the story when it comes to performance improvements; efficiencies such as better bus utilization is also a benefit of DDR5. “We want to keep that data bus constantly utilized.” By having more banks available to the system to refresh operations concurrent to data accesses, DDR5 offers a huge performance gainer over DDR4, he said.