Teardown: A Look at IBM Power9’s Micro-Architecture

Article By : Jeongdong Choe

A teardown of IBM's Power9 14HP DTC SOI FinFET eDRAM shows several significant technological changes from the company's preceding Power8.

IBM’s latest upgrade to its leading-edge commercial processors is the new Power9. These are the chips designed for use in the most advanced supercomputers, and for the most demanding data center workloads. IBM says its Power9 has up to 1.5x the performance of its Power8 predecessor, bolstered by the most advanced I/O subsystem technology the company could devise. What follows is TechInsight’s technical evaluation, which peers into the workings of one version of the Power9.

IBM adopted a new micro-architecture for Power9 such as 14 nm FD-SOI FinFET combined with a deep trench capacitor for eDRAM L3 cache memory, which enables ultra-dense eDRAM cell array, SCE and performance improvement, very low latency and keeping retention specifications. IBM is aiming to scale down the next-generation Power10 to 10 nm or even 7 nm for more performance improvement and latency reduction.

This article presents a summary of an analysis performed by TechInsights on the IBM 14HP HKMG FD-SOI FinFET eDRAM cell architecture, process, and design recently used in the IBM Power9 processor.

The IBM Power9 02CY297 FC-PLGA component consists of a NIMBU52C processor die with eDRAM blocks for L3 cache, fabricated by Global Foundries (GF). A deep trench capacitor (DTC) and SOI eDRAM cell design, replacing SRAM, is one of IBM’s core solutions for high-density and high-performance cache memories on IBM Power and System-z processors; however, the recent 14HP DTC SOI eDRAM cell design is quite different from their previous 22 nm SOI technology.

Figure 1 shows DTC eDRAM technology node and cell size trends from IBM to date. IBM/GF have adopted and employed the use of the DTC structure for eDRAM (DTC eDRAM or DT eDRAM named) cache area since it was first introduced in 45 nm eDRAM. The IBM Power8 22 nm DTC eDRAM cell consists of SOI/BOX and gate-first HKMG, while the IBM Power9 14 nm DTC eDRAM cell is designed with FinFET plus HKMG RMG (Replacement Metal Gate) access gates (WLs).

Figure 1. DTC eDRAM technology node and cell size trends from IBM up to date.

TechInsights’ eDRAM analysis on the IBM Power9 processor turned up a list of new GF innovations, especially in the areas of architecture, process, materials and design:

  • Global Foundries fabbed 14HP FD-SOI
  • 3rd HKMG eDRAM
  • 1st FinFET eDRAM with RMG
  • 4th Deep Trench Capacitor (DTC) eDRAM
  • eDRAM for L3 cache
  • 0174 µm2 SOI DRAM bit cell with 8F2
  • DTC eDRAM cell capacitance (estimated) ~8.1 fF/cell with ULK HfO/SiON high-k dielectrics and DTC depth 3.5 µm
  • DTC process for both cell capacitors and decoupling capacitors
  • Dual epitaxial layers for eSiC (eDRAM cell word lines and NMOS gates) and eSiGe (PMOS Gates)
  • 17 metal levels in total (excluding Al UBM connection layer)
  • 64 nm 1X M1 through M5 pitch, 2X M6 through M9, and 4X M10 and M11
  • ULK dielectrics for M1 through M9 ILDs, while LK ILDs for M10 through M15

The IBM Power9 processor 14HP FD-SOI DTC eDRAM with 8F2 unit cell size measures 0.0174 µm2 and is the first generation FinFET eDRAM cell architecture combined with DTC structure. After the SOI fin and dual epitaxial growth process on S/D area, HKMG RMG process integration is followed with multi-layered work-function materials both on eDRAM cell WLs and peripheral NMOS/PMOS gates. The FinFET/Gate process flow is different from that of the previous 22 nm gate-first eDRAM. They keep SOI wafer for eDRAM to minimize the parasitic capacitance at the base of the fin, body effect, and leakage current as well.

Table 1 shows a comparison of the eDRAM cell design and structure between the IBM Power8 (22 nm) and Power9 (14 nm). From TechInsights’ structure and materials analysis, we can estimate the DTC cell capacitor with ~ 8.1 fF/cell which is about 4 fF/cell lower than IBM Power8 22 nm DTC eDRAM cell. We are not yet sure of the accurate eDRAM cell capacitance (per trench) to satisfy L3 cache operation and retention requirement, but we estimate that it is a 30% reduction from that in the 22 nm DTC.

DTC = deep trench capacitor. eSiC = in situe doped epitaxial Si:C (C cannot be detected due to a very low doping level of ~E15/cm3)

The deep trench structure is also used for on-chip voltage supply decoupling with the same dimension and materials as cell capacitors. A very thin HfO layer is selected for the DTC high-k dielectric material together with SiON for MIS capacitor. HfO has a very high k constant (~25), while the thin SiON layer has likely been added to increase the thermal stability of dielectrics (Bandgap 6.5 eV) and CB offset as well. A very conformal 5.8 nm thickness TiN Atomic Layer Deposition (ALD) process is used for the top plate of the capacitor. Poly-Si strap patterns are heavily As doped and used to connect the DTC to the access device, which is the same design as in the previous 22 nm eDRAM.

As shown in Table 1, we can compare the process flow (sequence); 14 nm FinFET SOI eDRAM vs. 22 nm planar SOI eDRAM. The planar SOI eDRAM cell needs channel doping and halo implantation, while the 14 nm FinFET FD-SOI eDRAM cell does not need them, meaning the 14HP eDRAM cell channel is undoped. HfO gate oxide, TiAlC/TiN-based WF layers and TiAlO/W gate fillers are integrated for eDRAM access gate on active fin.

A summary of BEOL Cu metal levels, pitches and ILD layers is shown in Table 2. The IBM Power9 processor die consists of 17 metal layers in total with all the Cu materials used, which is an increase over the previous 15. IBM Power8 Cu metal layers routed with 80 nm 1X for M1 through M5 and 1.8X for M6 through M7, while IBM Power9 metal layers are designed with 64 nm 1X m1 through M5 and 2X for M6 through M9. M1 design scaled down by 20%. SiOF-based LK and SiOC-based ULK materials are used for each BEOL ILD layer.

This article was written using the information provided in TechInsights analysis of the IBM 14HP HKMG FD-SOI FinFET eDRAM, which can be found in two reports:

Both reports are available through TechInsights’ Embedded and Emerging Memory Subscription.

— Jeongdong Choe, Ph. D., is a Senior Technical Fellow at TechInsights

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