TSMC Expansion in Arizona to Focus on 3nm Node
TSMC sets its sight on 3-nm node production in second Arizona fab.
Synopsys Unveils Achievements on TSMC N3E Process
Synopsys' latest achievements in EDA and IP on the TSMC N3E process provide customers with robust solutions that help them…
Cadence Design Flows Now Certified for TSMC’s Latest N4P and N3E Processes
TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.
TSMC Reduces Expansion Plan to $36B as Outlook Dims
TSMC is cutting its 2022 capacity expansion budget in response to lower demand from smartphone and other consumer electronics makers.
Memory Market Collapse to Propel TSMC to Top Spot in 3Q22 IC Ranking
IC Insights expects foundry giant TSMC to surpass Samsung and take over the top spot in the semiconductor company sales…
TSMC Trims Expansion Plans as Outlook Dims
TSMC has lowered its expectations to spend more than $40 billion this year for capacity expansion due to predictions of…
TSMC Japan Completes Clean Room Construction in AIST Tsukuba Center
The TSMC Japan 3DIC R&D Center will pursue research into next-gen three-dimensional silicon stacking and advanced packaging technologies in materials…
TSMC Creates Design Options for New 3nm Node
TSMC's 3nm technology, starting production later in 2022, will feature the company's FinFlex architecture offering choices of standard cells with…
Synopsys Unveils RF Design Flow for TSMC N6RF Process
Synopsys' new RF design flow, developed with Ansys and Keysight for the TSMC N6RF process, boosts 5G SoC development productivity.
Siemens Extends Support of Multiple IC Design Solutions for TSMC’s Latest Processes
Siemens' ongoing collaboration with TSMC has resulted in new product certifications for several of its most advanced toolsets.
TSMC Expects $44B in Capex Despite Slowdown Concerns
Despite concerns that overall demand for chips may wane, TSMC is committed to spending more than $40 billion this year…
Industry Leaders Join Forces to Standardize Chiplet Ecosystem
Industry leaders have formed a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem.
