2022-11-21 - Maurizio Di Paolo Emilio

Electromagnetic Simulation Tools Help Optimize Chip Design

EM simulation tools can help accelerate on-chip design cycle times.

2022-10-31 - EE Times Asia

Synopsys, Ansys and Keysight Develop mmWave Reference Flow for TSMC Process Technology

Keysight, Synopsys, and Ansys have developed a mmWave design reference flow for TSMC's 16nm FinFET Compact (16FFC) technology.

2022-10-28 - Taiwan Semiconductor Manufacturing Co. Ltd

TSMC Expands OIP Ecosystem with Launch of 3DFabric Alliance

TSMC is expanding its OIP ecosystem with the launch of the 3DFabric Alliance at the 2022 Open Innovation Platform Ecosystem…

2022-10-28 - Synopsys Inc.

Synopsys Unveils Achievements on TSMC N3E Process

Synopsys' latest achievements in EDA and IP on the TSMC N3E process provide customers with robust solutions that help them…

2022-10-26 - Cadence Design Systems Inc.

Cadence Design Flows Now Certified for TSMC’s Latest N4P and N3E Processes

TSMC has certified Cadence's digital and custom/analog design flows for the latest N4P and N3E processes.

2022-10-20 - Cadence Design Systems Inc.

Cadence and Samsung Foundry Expand Collaboration to Advance 3D-IC Design

Through the continued collaboration, the reference flow featuring the Cadence Integrity 3D-IC platform has been enabled to advance Samsung Foundry's…

2022-10-19 - NeoLogic

NeoLogic Takes Processors Beyond Moore’s Law

NeoLogic's chip design technology is fully compatible with the existing manufacturing as well as EDA tools so it can seamlessly…

2022-10-12 - Sally Ward-Foxton

At Ayar Labs, It’s All Coming Together

An EE Times Exclusive interview with Ayar Labs CEO Charlie Wuischpard explores the future of optical chip-to-chip interconnects.

2022-10-10 - Alan Patterson

US Adds Limits on Chip Tech Exports to China

Citing national security concerns, the DoC has added more limits on exports of chips and related production tools to China.

2022-08-02 - Gary Hilson

Avery Introduces Chiplet Verification IP

Avery Design Systems' verification IP support follows recent formalization of the UCIe chiplet standard in a bid to provide pre–silicon…

2022-07-18 - Chouki Aktouf

Complex SoC Eco-Design Requires Unified Project Management

Beyond cost, eco-design is a dimension of SoC design that EDA tools can no longer ignore.

2022-06-20 - imec

imec Demonstrates Backside Power Delivery with Buried Power Rails for Back- and Frontside Routing

The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm…