Synopsys Unified Circuit Simulation Workflow Tackles SoC Design Complexity

Article By : Nitin Dahad

Synopsys is offering a unified approach to SoC design, accommodating complex mixes of analog, digital and mixed signal components.

With chip design becoming increasingly complex with multiple components and technologies coming together in hyper-convergent integrated circuits (ICs), a single system approach to analyzing the system would be a logical way of simplifying the complexity. Synopsys is addressing this with a unified circuit simulation workflow, PrimeSim Continuum, to deal with both the complexity and scale of today’s heterogeneous architecture chips for memory, artificial intelligence (AI), automotive and 5G applications.

Launched at the SNUG World international user conference, PrimeSim Continuum is an all-in-one solution consisting of simulation engines including PrimeSim SPICE, PrimeSim Pro, PrimeSim HSPICE and PrimeSim XA. This design environment delivers a seamless simulation experience around all PrimeSim engines with comprehensive analysis, improved productivity and ease of use. It forms the foundation of the Synopsys custom design platform.

Today’s hyper-convergent systems on chip (SoCs) consist of disparate components integrated onto the same die or package. These might include larger and faster embedded memories, analog front-end devices and complex I/O circuits that communicate at 100Gb+ data rates with the DRAM stack connected on the same piece of silicon in a system-in-package design. This diverse set of analog, digital and mixed signal components, some built on different process nodes, and possibly also integrated vertically using 2.5D or 3D architectures present even more complexity.

Synopsys PrimeSim_Continuum addressing complexityCircuit simulation needs to address both systemic complexity and scale complexity. (Source: Synopsys)

These challenges associated with verifying these complex designs scale as advanced technology process nodes present increased parasitics, process variability and reduced margins. This results in more simulations with longer runtimes at higher accuracy impacting the overall time to results, quality of results and cost of results.

Speaking to, Hany Elhak, group director of product management at Synopsys, said, “To address this, you need a system of simulation engines with unified workflow. There is no one SPICE simulator currently that can handle everything.” He said it is necessary to deal with both systemic complexity and scale complexity of IC designs.

This is what PrimeSim Continuum is meant to tackle. It addresses the systemic complexity of such hyper-convergent designs with a unified workflow of sign-off quality simulation engines tuned for analog, mixed-signal, RF, custom digital memory designs. PrimeSim Continuum uses next-generation SPICE and FastSPICE architectures and heterogenous computing to optimize the use of CPU and GPU resources and improve time to results and cost of results.

Synopsys PrimeSim_Continuum block diagramPrimeSim Continuum comprises simulation engines including PrimeSim SPICE, PrimeSim Pro, PrimeSim HSPICE and PrimeSim XA. This design environment delivers a seamless simulation experience around all PrimeSim engines. (Source: Synopsys)

As an example of the circuit simulation needs of complex designs, consider the emergence of high-bandwidth memory (HBM) consisting of large 3D stacked DRAM integrated with the SoC on a 3DIC or in a SiP. The HBM, which provides a high-speed memory interface for 3D stacked synchronous DRAM (SDRAM), is used with high-performance graphics accelerators, AI ASICs and FPGAs in high-performance datacenters and network devices. In these memory chips, multiple DRAM dies are vertically stacked with a memory controller, all interconnected by through-silicon vias (TSVs) and microbumps on a silicon interposer.

Designers need to verify the entire memory sub-system present in a SiP, which means performing complex multi-dimensional analysis at the component and sub-system levels. There are difficult and more stringent constraints with new complexities that must be addressed to achieve power and performance targets. Circuit simulation tools need to be able to support:

  • Analysis of multiple technologies and multiple components (logic, analog, memory, I/O)
  • Different types of analyses (analog, digital, mixed-signal)
  • Large capacities for sub-system and chip-level analysis
  • Advanced reliability analyses (electrical, thermal, electro-thermal, temporal)
  • Signal integrity
  • Variability analysis (process, structural)

In addition, as these designs scale to advanced technology nodes, there is a substantial increase in simulations to ensure that the design will be reliable and meet yield targets. Challenges include measurement of signal integrity, for example, which will need to be analyzed through the interposer. Issues such as electrothermal stress and larger parasitics must be addressed to foster chip reliability that manufacturing at scale will require.

From a design enablement perspective, this presents a multi-dimensional challenge that calls for workflows optimized for power, performance, area (PPA) and cost convergence.

Sassine Ghazi, chief operating officer for Synopsys, said, “PrimeSim Continuum represents a revolutionary breakthrough in circuit simulation innovation with heterogeneous compute acceleration on GPU/CPU, setting a new bar for EDA solutions. Our customers across every design segment can now benefit from years of R&D investment, innovation and customer collaboration with PrimeSim Continuum next-generation technologies that complement our modern custom design platform and Verification Continuum.”

Elhak said that Kioxia is an example of an early access customer that is using every aspect of the new solution, with flash memory being a very complex system. Kioxia memory designs integrate complex systems consisting of memory, analog, mixed-signal and custom digital blocks that require different design and signoff technologies.

Shigeo (Jeff) Ohshima, technology executive for SSD application engineering at Kioxia, said, “A converged workflow around a common circuit simulation solution is needed to meet our time-to-results and cost of results targets. Synopsys’ PrimeSim Continuums is an all-in-one solution that integrates the best SPICE and FastSPICE technologies delivering accuracy, speed and capacity for our complex designs. The PrimeWave design environment provides a common workflow across all simulation disciplines enabling the signoff of Kioxia’s memory designs. Effective collaboration and access to next-generation technologies are fundamental to our partnership with Synopsys.”

PrimeSim Pro for performance acceleration

Synopsys PrimeSim Pro simulator, a part of PrimeSim Continuum, represents a next-generation FastSPICE architecture for fast and high-capacity analysis of modern DRAM and Flash memory designs.

Continual technology scaling and innovations around DRAM architecture have resulted in larger and more complex memory designs requiring higher simulation performance and capacity. According to Jung Yun Choi, corporate vice president of the memory design technology team at Samsung Electronics, said,“Synopsys PrimeSim Pro, the next generation of our plan of record FastSPICE simulator, can deliver up to 5X performance acceleration on our full-chip power delivery network designs. PrimeSim Pro next-gen architecture can keep pace with the capacity needs of our advanced memory designs and allow us to meet our aggressive time-to-results targets.”

Nvidia the partner and customer

Synopsys PrimeSim SPICE simulator’s next-generation architecture with uses Nvidia’s GPU technology to deliver significant performance improvements needed to perform comprehensive analysis for analog and RF design while meeting signoff accuracy requirements.

“As modern compute workloads evolve, the size and complexity of analog designs have moved beyond the capacity of traditional circuit simulators,” said Edward Lee, vice president of mixed signal design at Nvidia. “Using NVIDIA GPUs enables PrimeSim SPICE to accelerate circuit simulation, notably minimizing signoff time of analog blocks from days to hours.”

“As design complexity increases with advanced process nodes, we are committed to supporting our mutual customers with innovative simulation technologies to reduce verification and analysis cycles,” said Jaehong Park, executive vice president and head of foundry design platform development at Samsung Electronics. “Synopsys PrimeSim Continuum with its unified workflow of advanced simulation engines delivered 10X speed up with golden SPICE accuracy using heterogeneous compute acceleration on our recent 56Gbit Ethernet design, reducing verification efforts from days to hours.”

Unified workflow for analysis and signoff

The PrimeSim Continuum solution integrates PrimeSim SPICE and PrimeSim Pro with the PrimeSim HSPICE simulator, the gold-standard signoff reference for foundation IP and signal integrity and the PrimeSim XA simulator, the FastSPICE technology for SRAM and mixed-signal verification. PrimeWave delivers a seamless experience by providing a consistent and flexible environment across all PrimeSim Continuum engines optimizing design set-up, analysis and post-processing.

This article was originally published on Embedded.

Nitin Dahad is a correspdondent for EE Times, EE Times Europe and also Editor-in-Chief of With 35 years in the electronics industry, he’s had many different roles: from engineer to journalist, and from entrepreneur to startup mentor and government advisor. He was part of the startup team that launched 32-bit microprocessor company ARC International in the US in the late 1990s and took it public, and co-founder of The Chilli, which influenced much of the tech startup scene in the early 2000s. He’s also worked with many of the big names – including National Semiconductor, GEC Plessey Semiconductors, Dialog Semiconductor and Marconi Instruments.

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