Synopsys Launches Industry’s Highest Performance Neural Processor IP

Article By : Synopsys Inc.

Synopsys' new DesignWare ARC NPX6 NPU IP delivers up to 3,500 TOPS performance for automotive, consumer, and data center chip designs.

Addressing increasing performance requirements for artificial intelligence (AI) systems on chip (SoCs), Synopsys Inc. has launched a neural processing unit (NPU) IP and toolchain that delivers the industry’s highest performance and support for the latest, most complex neural network models. Synopsys DesignWare ARC NPX6 and NPX6FS NPU IP address the demands of real-time compute with ultra-low power consumption for AI applications. To accelerate application software development for the ARC NPX6 NPU IP, the new DesignWare ARC MetaWare MX Development Toolkit provides a comprehensive compilation environment with automatic neural network algorithm partitioning to maximize resource utilization.

“Based on our seamless experience integrating the Synopsys DesignWare ARC EV Processor IP into our successful NU4000 multi-core SoC, we have selected the new ARC NPX6 NPU IP to further strengthen the AI processing capabilities and efficiency of our products when executing the latest neural network models,” said Dor Zepeniuk, CTO at Inuitive, a designer of powerful 3D and vision processors for advanced robotics, drones, augmented reality/virtual reality (AR/VR) devices and other edge AI and embedded vision applications. “In addition, the easy-to-use ARC MetaWare tools help us take maximum advantage of the processor hardware resources, ultimately helping us to meet our performance and time-to-market targets.”

Advanced driver assistance systems (ADAS), surveillance, digital TVs and cameras and other emerging AI applications that implement complex neural network models are putting greater demands on compute and memory resources, often for safety-critical functions. To address the range of application requirements, the ARC NPX6 NPU IP:

  • Scales from 4K to 96K MACs
  • Delivers, in a single instance, up to 250 tera operations per second (TOPS) at 1.3 GHz on 5nm processes in worst-case conditions, or up to 440 TOPS by using new sparsity features, which can increase the performance and decrease energy demands of executing a neural network
  • Integrates hardware and software connectivity features that enable implementation of multiple NPU instances to achieve up to 3,500 TOPS of performance on a single SoC
  • Provides more than 50x the performance of the maximum configuration of the ARC EV7x Processor IP
  • Offers optional 16-bit floating point support inside the neural processing hardware, maximizing layer performance and simplifying the transition from GPUs used for AI prototyping to high-volume power- and area-optimized SoCs

DesignWare ARC NPX6FS NPU IP meets stringent random hardware fault detection and systematic functional safety development flow requirements to achieve up to ISO 26262 ASIL D compliance. The processors, with comprehensive safety documentation included, feature dedicated safety mechanisms for ISO 26262 compliance and address the mixed-criticality and virtualization requirements of next-generation zonal architectures.

The ARC MetaWare MX Development Toolkit includes compilers and debugger, neural network software development kit (SDK), virtual platforms SDK, runtimes and libraries, and advanced simulation models. MetaWare MX offers a single toolchain to accelerate application development and automatically partitions algorithms across the MAC resources for highly efficient processing. For safety-critical automotive applications, the MetaWare MX Development Toolkit for Safety includes a safety manual and a safety guide to help developers meet the ISO 26262 requirements and prepare for ISO 26262 compliance testing.

Synopsys’ broad DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Our extensive investment in IP quality and comprehensive technical support enable designers to reduce integration risk and accelerate time-to-market.

 

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