Startup Stacks IoT Chips Cheaply

Article By : Rick Merritt, EE Times

Startup zGlue designed a low-cost 2.5-D substrate for integrating more than a dozen chips, providing an alternative to SoCs for the Internet of Things.

SAN JOSE, Calif. — A startup emerged from stealth mode with a low-cost approach to building 2.5-D chip stacks that target the Internet of Things. zGlue developed a substrate that can link more than a dozen die as an alternative to designing a more expensive and time-consuming SoC or a much larger circuit board.

“It takes too much time to customize chips today,” said Ming Zhang, founder and CEO of zGlue and a veteran circuit design who worked on Intel Xeon and Samsung Exynos processors. “I wanted to enable chips useful for a large IoT market, including many who may not understand things like timing closure and through silicon vias.”

The startup is one of many companies using novel packaging to make up for the increasing complexity and cost of CMOS scaling. To date, most chip stacks have been too expensive for anything but the most high-performance devices, but many companies are working on lower-cost options.

zGlue uses a trailing-edge interposer of 24 to 48 mm2 with integrated passives as well as a controller supporting power management and security. Its chip-to-chip interface can be configured in software and can accommodate most packages but is optimal for WLCSPs.

The interposer supports up to 3,000 programmable interconnect pins. SPI and GPIO interfaces can run at up to 100 MHz and UART and I2C interfaces at lower rates. It supplies power to chip-lets at 1.8 V and 3.3 V by default, adjustable to 100 mA max current.

“The interposer takes care of all system functions beyond what the chip-lets are doing … [and it supports] multiple power rails to MCUs and sensors … and absorbs into the substrate PMICs [that] you would otherwise have to buy,” said Zhang. “Users can turn off or on functions based on their needs such as encrypted interconnects, anti-tampering checks, and a transaction security engine.”

The approach is optimal for devices that would use at least four chips and probably no more than 30. “We can comfortably address a normal spectrum of system complexity for AR/VR, industrial, and medical systems.”

zGlue would not say what process it uses for its interposer. (Images: zGlue)

zGlue would not say what process it uses for its interposer. (Images: zGlue)

The company has a working prototype and expects to be ready for volume production early next year at an unnamed foundry and assembly house. It is currently ramping its first product, designed for BOE Technology Group Co. Ltd., a systems company in China.

zGlue aims to serve both large companies who will want to work directly with the foundry and assembly house and smaller companies who will define products that they let the startup oversee.

In either case, customers provide a port-to-port schematic of their design using a streamlined EDA tool from zGlue called zCAD. The tool handles placement and routing of interconnects, electrical checks, and optimization.

The startup also has ambitious plans to create an online store of chips available for use with its technology. It aims to launch the Ziplet store this fall with links to sensors, microcontrollers, memory, and communications chips from multiple vendors.

“There are a lot of suppliers out there, but we aim to boil this ocean in a smart way, in part leveraging customer pull,” said Zhang.

The startup’s road map includes a second phase that will enable security and advanced power management in the fabric as well as additional test features. A third phase will support in the fabric high-bandwidth memory as well as integrated flash and sensors.

So far, zGlue has raised two funding rounds and hired more than 30 people. It needs another round still in the planning stage to enable volume production.

The startup first emerged in May 2015 as one of a handful of companies working with Silicon Catalyst, a semiconductor startup incubator in Silicon Valley. zGlue’s co-founders have backgrounds as chip designers at Sun, AMD, and TSMC, and its China manager was an architect at Apple and Fitbit.

— Rick Merritt, Silicon Valley Bureau Chief, EE Times Circle me on Google+

Related posts:

[Article originally posted on EE Times.](

Subscribe to Newsletter

Leave a comment