Eliyan Corporation’s chiplet interconnect cost-effectively connects homogeneous and heterogenous architectures on standard organic substrate.
Chiplets are getting a lot of interest as of late, so much so that a Universal Chiplet Interconnect Express (UCIe) consortium recently formed to corral best practices into a standard. Now, a Silicon Valley startup, Eliyan Corporation, is coming out of stealth mode to show it can contribute to the chiplet ecosystem with a more efficient approach to packaging.
Eliyan’s high-performance chiplet interconnect addresses what the company believes is a critical need for a cost-effective way of connecting homogeneous and heterogenous architectures on a standard organic substrate, Eliyan CEO Ramin Farjadrad said in an interview with EE Times.
The “bunch of wires” (BoW) chiplet system can achieve similar bandwidth, power efficiency and latency as die-to-die implementations using advanced packaging technologies by using standard packaging, he said. “It opens up the door to significant possibilities and eliminates all the drawbacks and limitations of advanced packaging.”
The end of Moore’s Law can be offset by chiplet-based systems-in-package (SiPs), which are enabled by abundant parallelism and multi-chip integration. Chiplet-based SiPs also have a smaller footprint, are less expensive and consume less power — all while delivering high performance.
The Open Compute Project (OCP) adopted the BoW scheme, which includes Eliyan’s NuLink PHY and the patented NuGear 2.5/3D topology solutions. The NuLink technology is backward-compatible with UCIe, a standard developed by Intel that covers the die-to-die I/O physical layer, die-to-die protocols and a software stack model leveraging PCI Express (PCIe) and Compute Express Link (CXL) industry standards. Intel donated the UCIe standard to the recently formed UCIe Consortium.
Eliyan specifically developed the BoW approach to address the need for highly efficient die-to-die PHYs to connect different functions in one package, which is critical for realizing the scale of performance and integration required by a broad range of compute-intensive applications for data centers, cloud computing, artificial intelligence and graphics.
The company’s NuLink PHY technology is a superset of BoW and UCIe that uses patented implementation techniques to provide major power-performance differentiation for die-to-die connectivity over any packaging substrate, reducing complexity and lowering overall development time and costs.
“Our solution can be applied to any chip systems,” Farjadrad said. “We basically eliminate the need for advanced packaging.”
Those advanced packaging solutions eliminated by NuLink include silicon interposers and embedded multi-die interconnect bridges (EMIBs). Silicon interposers, for example, require an extra piece of silicon. “That limits the real estate that you can put these chips,” Farjadrad said.
Because silicon interposers limit overall SiP size, they can in turn limit performance, result in low wafer test coverage that ultimately impacts yield, increase total cost of ownership and extend production-cycle times, he added. “That’s a big limitation.”
Although the high-trace density of EMIBs enables high inter-chiplet bandwidth at low power, as well as large and complex systems, they are also higher in cost with a lower test coverage and yield, Farjadrad said. EMIBs also extend production cycles and have limited routability and reach.
Eliyan’s Nulink PHY provides the necessary BoW to eliminate silicon interposers and connect HBM3 to ASIC on an organic substrate to support many HBMs and ASICs required for high-performance computing and AI. The BoW approach also enables long die-to-die interfaces to reach reduced packaging complexity and cost, as well as low manufacturing cycle times. “We don’t need to build fancy high-speed circuits in between these two chips,” Farjadrad said.
Along with NuLink, Eliyan’s patented NuGear technology enables practical mix and match of chiplets with different die-to-die interfaces in varying processes, including DRAM. The company mass-produced an earlier version on a 14-nm process to provide commercial viability and performance advantages, while the most recent version that was taped out at 5 nm delivers a minimum of 2,000 Gbps/mm of edge bandwidth on a standard organic package.
This article was originally published on EE Times.
Gary Hilson is a freelance writer and editor who has written thousands of words for print and pixel publications across North America. His areas of interest include software, enterprise and networking technology, research and education, sustainable transportation, and community news. His articles have been published by Network Computing, InformationWeek, Computing Canada, Computer Dealer News, Toronto Business Times, Strategy Magazine, and the Ottawa Citizen.