Deca knows new approaches are needed to continue to scale production, as well as to address the demands of "More than Moore."
Deca Technologies is relatively small by the behemoth standards of the IC packaging, assembly and test business, but they are pushing limits and enabling important new industry directions that might at least set a few records.
History — A serious pedigree
Tim Olson left Amkor in 2009 to found Deca Technologies. In his post as a senior VP at Amkor, Olson led the global research and development programs. Among other innovations while at Amkor, he introduced the package-on-package through mold via (PoP TMV) and fine-pitch copper flip chip for high volumes. These technologies are instantly recognizable for their impact in the last decade or so.
But that was not enough for Tim Olson. He saw the demands that would be placed on packaging technology going forward and realized that new approaches would be needed to continue to scale production as well as address the demands of the “More than Moore” (don’t forget: MTM) side of the semiconductor industry.
And the interest from big names is evident on the Deca board with packaging giant ASE Global’s Rich Rice, as well as representation from Qualcomm, Infineon, and Nepes. These companies have all invested, licensed Deca technologies, or both.
Cypress was the early investor putting up $100 million to launch Deca Technologies with wafer level panel (WLP) production at a package assembly plant outside Manila. With the industry connections and proven know-how, Tim Olson also attracted investment from SunPower. The Philippines plant assembled integrated circuits, but Deca actually used equipment originally designed for printed circuit board and solar cell manufacturing.
This bit of the Deca story was courtesy of discussions with CTO Craig Bishop, who took time out to relate the history to me. Craig patiently helped me through the technical part of the Deca Technologies story as well.
M-series fanout packaging
The wafer-level package (WLP) has become a popular approach that provides a smaller footprint (particularly thickness) compared to substrate-based packages while reducing the bill of materials and cost of production. Using an extremely simplified explanation, the technique creates a component only the size of the integrated circuit chip that can be assembled onto a final system board by adding an interconnect layer (the redistribution layer, or RDL) directly onto the silicon die. The RDL connects the pads on the silicon chip to sites for solder balls to allow direct placement of an integrated circuit die onto a circuit board with virtually no overhead.
This package type is known as a fan-in wafer level package (FIWLP) since the interconnect stays within the boundary of the integrated circuit die. But this can be extended for more complex products with more inputs and outputs by adding some molding material beyond the silicon die edges and deploying RDL beyond the chip boundary. This is known as the fan-out wafer-level package, or FOWLP.
FOWLP requires dicing the silicon wafer and then re-assembling these onto a carrier. The RDL can be created that spans the silicon die and beyond. This structure is then reconstituted into a wafer (or panel) be encasing the full die in epoxy mold compound (EMC). Individual packages are singulated out of the reconstituted wafer.
The major selling point for Deca and its M-series platform is the five or six side device encapsulation. Whatever the count, the die surfaces are protected by encapsulation. The M-series flow is available for the smaller fan-in designs and offers the same die edge protection of FOWLP boosting reliability of the smaller packages.
TSMC’s InFO (integrated fan-out) version of fan-out WLP is definitely the most well-known flavor of this technology. Like so much in the semiconductor business, the state of buzz is often related to Apple products. InFO is no exception with the Apple A-series processors adopting this TSMC package for the A10 in the IPhone7.
There are a couple of notable differences between the M-series and TSMC’s popular approach. Deca uses a chip first flow where the die is molded in a wafer panel prior to adding the RDL traces. Also, the InFo packages use a spin on coating to protect the die backside versus the epoxy mold encapsulation in the M-series.
After limited market success for WLCSP, Deca doubled down on the FOWLP. That attracted the interest of Qualcomm who provided capital for Deca and moved their PMICs to M-series production.
The Qualcomm PMIC business is substantial. There are a few in every Snapdragon-powered smartphone.
Squaring the circle
A central step to FOWLP and indeed the M-series (including FIWLP) process is the creation of a reconstituted wafer of singulated die. The die are placed on a carrier for the additional steps of molding, creating the RDL, and adding the external solder balls (and lots of steps left out for brevity).
Reconstituting a wafer is also referred to as panelization. Current production panels mimic the original size and shape of the silicon wafers. Today panelization creates a 300 mm round reconstituted wafer.
But we know chips are rectangular. There is a fundamental problem fitting a bunch of squares into a circle. (I’m sure there is an engineer joke in there, but I will spare you.) In wafer processing, some silicon area has to be given up near the edges. A similar problem exists with package panels. There is wasted space.
For traditional packaging on substrate or leadframes, the panels used for assembling chips into their final form have always been rectangular. It’s time wafer-level packaging catches up to the old way of doing things.
That is now happening. Deca has created the tooling design and flows for massive 600mm by 600mm panels. It is not the only panel size being developed though. Intel settled on 510mm by 515mm. Both are standards maintained by SEMI allowing equipment manufactures to build for them.
The wafer has been squared, so naturally the nomenclature must keep pace. The WLP is now the PLP or panel-level package. This is taking up too much headspace. Does this mean we need to replace FIWLP and FOWLP?
The Deca M-series equipment was designed from the beginning with square panels in mind or at least a straightforward upgrade path for moving to square panels.
Nepes is building a 600mm PLP facility in Korea. ASE is preparing for 600mm production in Taiwan. ASE has replaced the FOWLP acronym, but they deserve credit for the simplification. The 600mm PLP is known to them as Panel FO. Nepes and ASE have both licensed Deca technology for their operations.
Check back in a couple years. Not to see where the technology is, it will take time for the acronyms to settle out.
You won’t need to wait months or years to hear the rest of the Deca Technologies story. There’s a lot more than just big panels. Deca is developing techniques that are bound to accelerate high volume manufacturing of heterogeneous chiplet designs. Stay tuned for more on EETimes.