Spin-Orbit-Torque Tackles MRAM Constraints

Article By : Gary Hilson

Memory startup Antaios believes spin-orbit-torque MRAM will address the “trilemma” of data retention, endurance and write speed.

The next generation of embedded MRAM (magneto-resistive RAM) may boil down to changing the order of ingredients in the recipe.

Spin-orbit-torque (SOT) MRAM addresses the “trilemma” that Spin-transfer torque (STT) MRAM currently faces, said Antaios CEO Jean-Pierre Nozières in an interview with EE Times. The significant voltage across the device tunnel oxide that’s required for writing means there is a continual tradeoff between data retention, write endurance, and write speed. That means even though it’s reached near maturity, STT MRAM is still constrained when it comes to meeting the demands of high-speed RAM applications that require a combination of high speed and infinite endurance, along with acceptable data retention.

SOT-MRAM does not require passing of a high current through the magnetic device (the so-called Magnetic Tunnel Junction) during the Write operation, which is done by a current flowing through an adjacent “SOT” metal line. (Courtesy Antaios)

Founded in 2017, Antaios began ramping its development efforts on third generation MRAM in 2019 by using SOT, a spintronic effect, that shows a lot of promise in overcoming the constraints of STT-MRAM and other previous generations of the technology, without requiring major changes to manufacturing processes, said Nozières. SOT-MRAM solves the trilemma by fully eliminating the high voltage across the device tunnel oxide during write, which results in intrinsic unlimited endurance. “The current technology is limited to embedded flash replacements. You have the trilemma between retention, speed and endurance.” By removing this constraint, he said, it opens the door to replacing incumbent memories including flash and SRAM in applications for high-speed applications that previous generations couldn’t address.

Another inherent benefit of SOT-MRAM is that it eliminates data-retention leakage current and is impervious to ionizing radiation data disturbance, which are both severe issues for SRAM, said Nozières. SOT-MRAM write energy also promises to be favorably lower compared to STT-MRAM due to its very high-speed writing. “It’s a giant leap in terms of system level performance.”

One of the early applications for SOT-MRAM include CPU last-level-cache, either as part of a traditional embedded architecture, or as an alternate 3D assembly technique that leverages “die-on-die” from different wafers with different process for high-end CPUs with very large caches. Nozières said both are fully compatible with the SOT-MRAM process flow under development.

Another promising use case for SOT-MRAM is for artificial intelligence (AI) in edge devices, he said, of which most operate in von Neumann architectures and use large amounts of external, off-chip memory. On-chip SOT-MRAM could operate like a cache/working-memory for which speed and endurance are key while requiring significantly less power.

Microcontroller architectures could also benefit from SOT-MRAM. The current separate flash “control store” block and SRAM block architectures is akin to constantly shuffling books around on a bookshelf to accommodate additions. “You’re just swapping your books on the shelves, which takes a lot of time and energy,” said Nozières. “That’s exactly what’s happening inside the microcontroller.” Because SOT-MRAM can simultaneously achieve embedded flash-like data retention with main-memory read and write cycle times in the 10ns and faster range, it would allow for a single “execute-in-place” (XIP) block with substantial improvements in power, performance, and cost.

SOT is based on spin-transfer effects, just like today’s STT MRAM, except there is no need for a magnetic layer to spin-polarize the electrical current. The source of spins is simply the lattice of a SOT layer material via the spin-orbit interaction. (Courtesy Antaios) (Click on the image for a larger view.)

SOT-MRAM still has a long way to go, he said, but Antaios’ approach is not to do everything itself, but instead forming relationships, including on the manufacturing side. Last year it secured investment funding led by French venture capital firms Innovacom and Sofimac Innovation, together with Silicon Valley-based Applied Ventures, LLC, the venture capital arm of Applied Materials, Inc. Nozières said the company is looking to take advantage of the ecosystem around MRAM, noting that now defunct Spin Memory burned through a great deal of cash by trying to do everything, including manufacturing.

Today’s STT MRAM Like SOT is based on spin-transfer effects, but there is no need for a magnetic layer to spin-polarize the electrical current. The source of spins is simply the lattice of a SOT layer material via the spin-orbit interaction. This makes SOT a straightforward extension of today’s MRAM technologies already in production in major foundries, Nozières said, so there’s no need “evangelize” the market to spend hundreds of millions of dollars to implement new tools and new materials. He likens both STT-MRAM and SOT-MRAM to a BLT, only the order of the ingredients is different in each. But despite the simple analogy, SOT-MRAM is still in infancy, and the expectation is that SOT-MRAM might be available for commercial applications some time in 2024.

This article was originally published on EE Times.

Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.

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