SoC Interconnect: DIY Equals Danger

Article By : Kurt Shuler

With so many acquisitions in the interconnect IP market, you might be forgiven for thinking DIY interconnect is a good idea

There’s been a lot of action in the interconnect IP market over the past year – most notably the acquisition of NetSpeed by Intel and Sonics by Facebook. What’s happening? Why are companies seeing the critical importance of interconnect IPs now? Is interconnect a key factor in system-on-chip (SoC) delivery productivity for multi-SoC project corporations? Are these acquisitions a way around the fact that interconnect development is lengthy, costly, and difficult?

The recent market consolidation might have some companies considering whether this is a do-it-yourself (DIY) project that your company should consider taking on. Whether it’s a simple crossbar switch or a full-function network-on-chip (NoC) architecture for advanced SoCs, all that’s needed are the right people with the right knowledge and a big budget; eventually, it could happen. But the question isn’t can you do it? It’s should you do it?

Licensing NoC IP from a provider that already has a history of tackling cutting-edge issues, such as functional safety for autonomous vehicles, can help accelerate time-to-market with the right features, documentation, and traceability. (Source: Arteris IP, Arm)

SoC applications have rapidly changing requirements that must be quickly addressed through the interconnect, but most homegrown interconnects were not developed to be user friendly. Given the huge fixed development costs, doing one chip a year usually makes no economic sense. Most design teams have adopted a platform approach where one design is adapted for multiple markets and use cases by quickly creating derivative chips. The interconnect is key to creating these derivative semiconductors; failure to have a world-class interconnect IP slows down the ability to adapt to new chip requirements and severely limits the market responsiveness of companies.

Figure 1. SoCs for different markets and use cases can have very different NoC interconnect requirements and priorities. 100% quality is necessary no matter what type of SoC, though. (Source: Arteris)

Another important thing to consider is that building an interconnect is very difficult, given all of the power, latency, bandwidth, data path, and security parameters that need to be optimized. Not to mention the unique engineering expertise required to make an interconnect IP. Interconnect development is a team sport requiring a coherent combination of architecture, hardware, and software development expertise with meticulous attention to verification and quality. The bottom line is creating a configurable interconnect IP product that is scalable enough for nearly any SoC goes beyond skill; “it is an art,” and it’s becoming a critical art.

DIY = Danger
If you’re still tempted to build your own interconnect IPs, let’s take a moment to consider what it takes to develop NoC interconnects. NoC technology uses a packetized approach; it eliminates wires, frees up chip real estate, and reduces power demands. Designing the NoC so that it gets the packets to where they need to be, at the time they need to be there – without blowing up the area and/or power – this is the tricky part. This requires three distinctly skilled experts: The networking expert to break down packets, channels, and quality of service; the semiconductor expert for design, verification, and HDL expertise to design down to the gate level; and the software expert to ensure that the configuration tooling provides as much information and automation as is required to create an efficient and, hopefully, pleasurable experience for the chip architects and interconnect implementers who are driving the interconnect configuration. And remember, interconnect IP quality is essential because bugs in the interconnect can cause project delays or even failures. This means that effective quality processes and execution are key to interconnect IP delivery.

In reality, it takes up to 30-50 engineers to develop a NoC and the team will, in all likelihood, be weak in one of the three key areas. If the time to market is not a concern, this team may get there, eventually. And funding is a key constraint because internal interconnect teams are often starved of resources as they are forced to develop custom interconnects for specific SoC projects rather than develop a broad, long term solution. Today’s chip market is changing more rapidly than designers are able to adapt–as soon as one NoC is done, new requirements emerge and it’s back to the drawing board for the next chip iteration to meet new goals for performance, bandwidth, cache coherence, arbitration, latency, quality of service, power management, and security. Invariably, the internal development interconnect team becomes the corporate constraint on the amount of time it takes to ship a chip that meets requirements.

By the time a design team reaches the pain threshold and decides to switch to an interconnect IP licensing model, the market opportunities for their chips may have come and gone; it’s a very Darwinian business. The biggest fear of these teams is what will happen to the jobs of the current interconnect team if the company chooses to license the IP.

Oh, what a difference IP makes
An example of this comes from an Arteris IP customer. Before this chip company started working with us, they developed only four SoCs per year because it took them more than a month to implement any changes in an interconnect instance created by their internal bus group using their internally developed interconnect IP. Once the customer adopted a commercial interconnect IP, they were able to increase their chip output to over 20 designs per year, which allowed them to economically deliver market segment-tailored chips that captured additional design wins at good gross margins and acceptable prices to customers. What was most interesting to me was that even though the internal team had been creating “optimized” interconnects specifically for the customer for a decade, the new commercial IP solution outperformed theirs in every aspect, and it ultimately saved an average of 3 square millimeters of die area per chip versus the internally-developed interconnect. This savings is about 30 cents per chip, which means many millions of dollars at volume.

chip die


Today, rapid technology advancements in new technology markets have made commercial NoC interconnect IPs even more important. This is especially true for two of the fastest growing markets: automotive and machine learning (ML)/AI. For automotive, the on-chip interconnect is a unique enabler for ISO 26262 functional safety compliance because it “sees” all the data traffic flowing through a chip and can flag, and sometime even correct errors before they become failures that affect system safety. For ML/AI chips and subsystems, the buzz is about neural network algorithms and how design teams make custom processing elements to hardware-accelerate the mathematical operations of these algorithms. But the real challenges come later: How do you keep the chip “fed” with data? If you answered “dataflow,” you are correct. And the on-chip interconnect is the most important IP responsible for optimizing the flow of data between the AI/ML processing elements, memories, and peripherals.

Changes in the automotive and ML/AI SoC markets are speeding up on-chip interconnect technology innovation just as its importance is exploding. The pace of change is too fast for any individual semiconductor company to keep up and expect to be world class. Fortunately, there are trusted specialists immersed daily in the art of interconnect IP technology. Licensing state-of-the-art on-chip interconnect IP from the experts is the best way to benefit from this accelerating innovation.

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