Chip makers will collaborate to develop a framework for testing time-sensitive capabilities in networking silicon and semiconductor IP.
A new chip industry group insists network interoperability is all in the precise timing.
The Avnu Alliance, the chip industry consortium promoting network interoperability, is launching a working group consisting of silicon and IP vendors promoting time-sensitive networking (TSN). The effort reflects the shift from legacy to deterministic networking driven by connected devices ranging from automotive to industrial applications.
Members of the new Silicon Validation Task Group include Analog Devices, Intel Corp., Keysight Technologies, NXP Semiconductors, Texas Instruments and TTTech.
“Software, applications and profiles can all be tailored to specific use cases, but they need a stable network foundation to build on top of,” said Greg Schlechter, president of the Avnu Alliance. Task group members will seek to “identify what TSN interoperability means for basic network components, and how we can get interoperable products to market.”
TSN is a set of Ethernet specs established by the IEEE along with an accompanying base standard, Audio Video Bridging. Among other goals, the industry consortium is intended to ensure that deterministic real-time communications protocols are baked into the next generation of Ethernet. That would allow the scheduling of traffic on switched networks while reducing network bottlenecks via what the group calls “bounded latency”.
New techniques for reducing latency are a must for the growing number of edge deployments and the large data volumes they generate. The alliance’s approach, Forward and Queuing of Time-Sensitive Streams, prioritizes time-sensitive data ahead of legacy “best-effort” packets. The approach not only ensures the delivery of time-sensitive streams but “ensures when they will arrive,” the group emphasized.
Silicon-level interoperability would foster “specialization further up the [technology] stack,” the group said this week, freeing product designers to leverage component and device interoperability for industrial and other edge applications.
“Ethernet’s universal success is centered around standards-based, interoperable silicon,” added Tom Weingartner, product marketing director for Analog Devices’ industrial Ethernet technology group. “As silicon providers, we are coming together to ensure this next generation of Ethernet with TSN is equally successful across the spectrum of silicon solutions.”
The Silicon Validation Task Group will develop a framework for testing TSN capabilities in silicon and chip IP “at the component and supporting software level,” the alliance said. The testing ecosystem would support industry collaboration in hopes of reducing product development timeframes while enabling the scaling of new networked devices.
This article was originally published on EE Times.
George Leopold has written about science and technology from Washington, D.C., since 1986. Besides EE Times, Leopold’s work has appeared in The New York Times, New Scientist, and other publications. He resides in Reston, Va.