A cohesive system takes hardware, software, and system verification to the next level of emulation and prototyping platform innovation.
The success of a system-on-chip (SoC) design is increasingly intertwined with the software performance, and that makes bridging the gap between hardware and software development flows critical. Not surprisingly, therefore, this era of software-centric SoC designs mandates dramatic changes in functional verification systems in the IC design realm.
The modern SoCs feature billion-gate designs, and their size and complexity are steadily growing. More importantly, while software performance drives SoC performance, long software sequences take extensive verification cycles to complete. Additionally, the SoC designers are increasingly using software workloads and benchmarks to verify power and performance.
MLPerf for AI chips and AnTuTu for mobile chips are a case in point. An accurate power and performance analysis during workload and benchmark cycles requires visibility to power activity, accurate analysis, and comprehensive debug tools. Siemens Digital Industries Software aims to address this semiconductor mega-cycle design conundrum with a new generation of verification solutions by creating a full suite of emulation and prototyping tools.
According to Jean-Marie Brunet, senior director of product management and engineering for emulation and prototyping at Siemens EDA, the company has expanded its Veloce family of products, formerly known as Veloce Emulator, to create a complete story. Below are the highlights of this design story.
Right tool for right task
SoC designers have to look at power and performance analysis, and then they have to run workloads, frameworks, and benchmarks to see how the SoC is behaving from power and performance standpoints. According to Brunet, that calls for a hybrid system that has all the key parts of the engineer’s verification toolbox.
“We have now all the pieces of the puzzle: virtual platform HYCON, Strato+ emulator offering full visibility of the chip, and versatility in the FPGA prototyping space with Primo and proFPGA platforms,” Brunet said while summing up the full suite of emulation and prototyping tools that encompasses big hardware boxes, desktop hardware, and software platforms.
A virtual platform for software-driven verification, Veloce HYCON provides SoC’s pre-silicon view, including software workload validation and characterization. It decouples software dependencies from hardware development, and software validation begins immediately.
“In a hybrid environment, SoC designers have less content on RTL and more content on the virtual model, and as a result, they can run software at 100’s of MIPS with the virtualized environment,” said Brunet. He added that the HYCON is the only solution on the market that enables early software workload analysis while being integrated into a hardware-assisted verification platform.
Moreover, after maximizing verification cycles, SoC designers can switch on the fly from this virtualized hybrid environment to an emulation platform that addresses the hardware team’s need for accuracy. And that brings us to the hardware emulator: Veloce Strato+.
A capacity upgrade to the Veloce Strato hardware emulator launched in 2017, Veloce Strato+ helps SoC developers cater to designs larger than 10 million gates, all the way to 15 million gates. “It offers a capacity improvement of 1.5x that works on the same chassis and facilitates a risk-free and pushbutton migration,” Brunet said.
He added that performance improvement comes to three things: compile, run and debug. Strato+ employs distributed architecture to leverage repetitive hierarchical designs and thus accelerate compile time. Next, it improves run-time with faster throughput and facilitates faster debug with 100% visibility.
AMD’s second- and third-generation EPYC processors have been qualified for use with Veloce Strato and Veloce Strato+ platforms. “When you perform verification of a chip of that size, capacity improvement is critical,” Brunet said.
When RTL reaches a level of stability, where debug is less critical, and performance is more important, IC designers can offload tasks from the emulator to an enterprise FPGA prototyping platform. “Now it’s all about speed and the need to run 5-10x faster than an emulator,” Brunet said.
Veloce Primo, an enterprise FPGA prototyping platform, provides much-needed scalability with a design capacity of up to 320 FPGAs. Simultaneously, it features consistency with the Veloce Strato platform with the same RTL, software workload, compiler model, and virtual environment.
Unlike Veloce Primo, targeted at large settings like data center, Veloce proFPGA addresses smaller capacity with individual access. “The footprint and size fit on a desk, usually at the lab, in a point-to-point setting for one user at a time,” Brunet said. On the other hand, Veloce Primo features enterprise access that is rack-based with multiple chassis and is much faster.
Veloce proFPGA is a modular system based on high-end FPGAs like Intel Stratix 10 GX 10M and Xilinx XCVU19P. Siemens EDA also announced that it has signed an OEM agreement for desktop prototyping with Pro Design.
All pieces of IC design puzzle
If SoC designers go right to prototyping, when the RTL is not debugged, they have to debug this in the prototyping engine. “Good luck with that because the prototype is not an environment for debug; it’s an environment for speed,” Brunet cautioned.
Nevertheless, the gradual transition from an emulator to an enterprise prototype environment is crucial, Brunet emphasized. Laurie Balch, research director at Pedestal Research, acknowledges that having an integrated suite of tools is valuable because it allows design teams to address a range of verification challenges from different angles without having to cobble piecemeal solutions.
She added that offering high capacity and configurability is how Strato+ and HYCON target the next generation of ever more densely packed and high-gate-count SoCs that need advanced emulation and prototyping tools at the early stages of the design cycle. “The model of hardware and software engineers operating in separate silos is no longer workable.”
That means the hardware must be knowledgeable about the software, and the software must be knowledgeable about the hardware from early on in the design process. For that, Siemens EDA claims, it has created a full suite of emulation and prototyping tools that encompasses big hardware boxes, desktop hardware, and software platforms.
This article was originally published on EE Times.
Majeed Ahmad, Editor-in-Chief at Electronic Design News (EDN), has covered electronics design industry for more than two decades. He holds Masters’ degree in telecommunication engineering from Eindhoven University of Technology. He has worked in various editorial positions, including assignments for EE Times Asia and Electronic Products.