By migrating its Solido Variation Designer usage to Arm-based processors on AWS, Arm was able to further reduce compute costs by 24%, total CPU time by 12%, and improve turnaround time by 6%.
Siemens Digital Industries Software’s machine learning (ML)-powered Solido Variation Designer software has helped Arm improve IP validation runtime by 1,000X compared to traditional brute force statistical methods, while achieving greater accuracy and coverage. This dramatic acceleration enabled Arm to verify its standard cell IP to Six Sigma, while significantly improving validation runtime.
“Improving compute cost and time-to-market is a constant priority for Arm, and we continue to meet and exceed high-quality and reliable operation requirements, enabling higher chip yield, performance, power, and area (PPA) metrics for our partners,” said Philippe Moyer, vice president of design enablement, Arm. “Solido Variation Designer helps Arm to deliver these benefits to customers by providing greater verification accuracy and coverage in a fraction of the runtime, and using AWS Graviton2-based instances powered by Arm Neoverse cores, we can further extend that advantage in cost-to-compute and turnaround time.”
By migrating its Solido Variation Designer usage to Arm-based processors on Amazon Web Services Inc. (AWS), Arm was able to further reduce compute costs by 24% and total CPU time by 12%, as well as improve turnaround time by 6%.
“As semiconductor IP validation workloads increase, access to cost-efficient and high-performance computing resources becomes a critical factor to meeting production schedules,” said Nafea Bshara, vice president and distinguished engineer, Annapurna Labs, AWS. “Solido Variation Designer running on AWS Graviton2 processors on AWS cloud is an example of Siemens driving greater scalability of semiconductor workloads and advancing innovation in the industry.”
Solido Variation Designer offers a comprehensive suite of tools for variation-aware design and verification. It uses machine learning methods to deliver fully accurate results while using orders-of-magnitude fewer simulations. This breakthrough technology enables Arm IP designers to verify designs more thoroughly and iterate revisions faster than before, resulting in high-yielding standard cell IP that helps customers achieve the aggressive PPA targets of today’s chip designs.
“Arm’s acceleration of IP validation cycles using Solido Variation Designer demonstrates the huge dividends that our investments in ML-powered technology are paying for our customers,” said Ravi Subramanian, Ph.D., senior vice president, IC Verification, Siemens Digital Industries Software. “We are pleased to have helped engineering teams at Arm to accelerate IP verification for their next generation of semiconductor products. In addition, this successful customer deployment on AWS Graviton2 processors demonstrates our commitment to working with the Arm ecosystem and cloud partners to deliver scalable solutions to mutual customers.”