7 Views of Globalfoundries in 2017

Article By : Rick Merritt, EE Times

Globalfoundries announced 12-nm FinFET and RF-SOI processes as part of an annual update on its road map.

SANTA CLARA, Calif. — Globalfoundries released a flurry of announcements at an annual gathering here, including an upgraded RF process and a 12-nm FinFET node. Analysts applauded the company’s growing capabilities but said that it mainly needs to deliver in the next 12 months a competitive 7-nm process and show a volume market for fully depleted silicon-on-insulator (FD-SOI).

“I had anticipated FD-SOI revenue this quarter, but it looks like it’s a little delayed … if it slips to Q4, that’s OK, but if it runs well into 2018, it could indicate a problem getting customers to adopt a technology that may have been overhyped,” said Len Jelinek, chief fab analyst for IHS Markit. “They have big plans for that technology in their Dresden and China fabs.”

“I’m waiting to see if they hit their plans for execution on 7 nm. That’s the first leading-edge process they are developing on their own,” said Nathan Brookwood of market watcher Insight64, noting that the company licensed its 14-nm process from Samsung.

Globalfoundries’ chief technologist, Gary Patton, said that those are, indeed, his two top priorities.

“We are very focused on our [FD-SOI] road map, both on the technology and the enablement for its body bias capability, and as for 7 nm, it is an extreme sport with tight process windows that will benefit from EUV,” said Patton in a press Q&A.


GF compared its high-end logic processes. Click to enlarge. (Images: Globalfoundries)

GF will start before June risk production of a 7-nm node using only immersion steppers doing “some quad and quite a few triple-patterning” layers, said Patton. It targets 60% greater density and 40% more performance than its 14-nm process and acks up to 17 million gates/mm2.

The foundry expects to phase in EUV in early 2019, initially just for vias and contacts. “My money is on 2020 for full use of EUV,” said Patton.

The big challenges still ahead are in finding a balance of performance and throughput for resists and getting defects out of masks. EUV mask yields are about 65% compared to 95% for all masks. Protective pellicles currently block 30% of the EUV light and need to get down to less than 10% — and none can currently withstand the projected 250-W EUV light source.

The good news is that FinFETs will still be useful for “one node beyond 7 nm, and then we’ll have to have something like nanowires,” said Patton.

The GF event came one week after TSMC gave an update on its road map.

Next page: Driving FD-SOI toward mainstream markets

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