Chipmakers now have a new manufacturing technology for more precise tungsten contact vias, which lead to performance, power, and area improvements...
Applied Materials has formally introduced its new Endura Volta Selective Tungsten CVD system that enables makers of semiconductors to selectively deposit tungsten in the transistor contact vias to reduce their resistance and increase transistor’s performance and cut its power consumption. Reduction of contacts’ resistance is crucial for modern and upcoming nodes that further shrink dimensions of transistors as well as contacts. The new tool, which is already in use by major makers of chips, promises to enable power, performance, and area for several upcoming generations of process technologies.
Contact resistance rises
Recent advances in production of semiconductors, such as multi patterning and extreme ultraviolet (EUV) lithography, have enabled chipmakers to shrink transistor sizes, increase their performance, and cut their power. These methods are set to enable further performance, power, and area (PPA) scaling for at least a decade. Along with transistors sizes, advances in lithography have shrunk dimensions of transistor contacts too, but tinier contacts mean higher resistance.
Furthermore, the way these contacts are formed make them so inefficient that at some point transistor contacts become bottlenecks for performance improvements and energy savings brought by new nodes. Essentially, transistors just starve for electrons and prevent chips from achieving their performance potential in normal conditions. As a consequence, chip designers have to increase currents and power consumption to actually extract that performance from their transistors.
Traditionally, tungsten conductors were grown within specially formed dielectric layers that consist of titanium/titanium nitride (TiN) liner/barrier and tungsten nucleation layers. The TiN layer ensures defect-free even growth and a complete gapfill of tungsten conductor, whereas the nucleation layer is required because tungsten cannot grow on TiN. The two cladding layers and the contact fill are formed in several steps using conventional chemical vapor deposition (CVD) method that deposits material across the entire wafer surface, which means poor control for sidewall adhesion (i.e., tungsten fill may delaminate) and growth (i.e., seams may form within the fill).
Transistor contacts scale with transistors and are getting narrower with every new node, but the two cladding layers — which are poor conductors when compared to bulk tungsten — stopped scaling nodes ago. Applied Materials says that the width of cladding layers — 5 nm for liner/barrier and for nucleation layers — remained essentially the same for several nodes now as they have reached their physical scaling limits. As a consequence, the contact resistance is going up with each new node.
“With the arrival of EUV, we need to solve some critical materials engineering challenges to enable 2D scaling to continue,” said Dan Hutcheson, CEO and chairman of VLSI Research. “Liner barriers have become our industry’s equivalent to arterial plaque, robbing the chip of the flow of electrons it needs for peak performance.”
At 14/16 nm nodes, the contacts were about 30 nm in diameter, including cladding layers. At 10 nm node, the contacts shrank to about 25 nm, based on Applied Materials’ estimates. With conventional contact formation methods at 7 nm, transistor contact via would have a diameter of only 20 nm, but ~75% of that volume would be used by liner/barrier and nucleation layers, which would leave only ~25% for bulk tungsten conductor (and would significantly increase resistance compared to previous-generation nodes).
Fighting unwanted resistance
Chipmakers and fab tool makers have strived to reduce unwanted resistance at transistor contacts for quite some time. To do so, they have attempted to shrink the volume of cladding layers and use new contact materials. In recent years, Applied Materials introduced its plasma-enhanced chemical vapor deposition (PECVD) process that replaces the traditional cladding layers with a tungsten-carbon film, it also offered a solution to prevent seam formation in tungsten conductors, and unveiled a cobalt-based fill.
In a bid to maximize performance and lower power, Intel used cobalt instead of tungsten for transistor contacts because it allowed making the TiN liner/barrier thinner and did not require a nucleation layer. Intel also moved to cobalt interconnects for some layers to reduce resistance of interconnects too. Some believe that because cobalt was a novel material for Intel several years ago, it was one of the reasons why the company faced tough challenges with its 10 nm technology. Meanwhile, this emphasizes how desperately semiconductor makers are trying to deal with chip resistances these days.
The means to reduce contact resistance have helped to improve performance and cut power consumption at post-14nm/16nm nodes, but they did not eliminate cladding layers completely, which is something logical to do.
“What we would ideally like to do now is to figure out a way to get rid of all of that ‘mold,’ free up all that volume and maximize the amount of space that we are actually using for the metal fill,” said Zhebo Chen, a global product manager in the Metal Deposition Products group at Applied Materials.
Selective Tungsten Deposition Process
Applied Material’s selective tungsten deposition process eliminates liner/barrier and nucleation layers completely and selectively fills contact vias with tungsten, thus increasing the volume of the conductor to 100% of the contact. Essentially, a transistor contact becomes what it is ideally meant to be, a pure metallic connection.
“In essence, it is kind of like going from a conventional fabrication approach now to […] almost like 3D printing at the atomic scale,” said Chen. “It is really just metal, exactly where you want it without needing any kind of mold at all. If you can do this, then you can really reset this entire curve. And you can allow the 2D scaling to continue for multiple generations.”
The selective tungsten deposition procedure relies on Applied Material’s Endura Volta Selective W CVD system. The high-precision process involves multiple steps as the tool applies atomic-level treatments to the wafer to remove all impurities and then makes tungsten atoms to selectively go to the bottom of the via therefore filling it from the bottom.
“It is a fully integrated material solution, which means that it takes place on our Endura platform, where we have integrated multiple processes in order to actually achieve this,” explained Chen. “So, it is not just a single process. In fact, it really [brings] together a number of different technologies into one tool in order to enable this capability.”
The bottom-up gapfill process eradicates delamination and seams and guarantees predictable resistance and high yields (as far as transistor contacts are concerned). Predictably high yields lower costs, which is something that both foundries and their clients ultimately want.
“So, there is a chamber that treats the metallic surfaces, there is a chamber that treats the dielectric surfaces, and then it goes to an actual [selective] deposition chamber that has been specially tuned in order to put that tungsten metal down on just the metallic surface,” said Chen. “Thus, making sure that it does not deposit anywhere you do not want it to in order to enable this bottom-up growth of tungsten.”
Endura Volta selective tungsten CVD
The Endura Volta Selective Tungsten CVD tool performs all process steps in multiple ultra-clean, high-vacuum chambers. The selective tungsten deposition process requires all steps to be performed in a vacuum environment, which means that the tool has to be fully integrated and perform all necessary process steps.
“We are really combining multiple process technologies into one product, one tool, all under this vacuum environment so you do not have that wafer having to travel between multiple tools and seeing an ambient environment,” the Applied Materials specialist explained. “Because the second you take that wafer…out into the air where it sees moisture or oxygen or various contaminants, this process is over. You cannot get it to work. So, it actually has to be fully integrated. That is one of the big key aspects of getting this to work in an actual HVM-type of environment here.”
According to the Applied Materials’ announcement, the Endura Volta Selective W CVD tool can perform operations that were not possible before and that the machine is ready to do so in a high-volume manufacturing environment processing thousands of 300-mm wafers.
The tool itself is fairly compact: it is approximately 5 m × 6 m, including service area around, so it is hardly going to be a problem for chipmakers to find space for it in a fab and integrate it into their production flows. Moreover, since the Endura Volta Selective W replaces traditional CVD tools (at least two tools are needed for conventional contact-forming CVD approach), its insertion into a process does not affect product cycles.
The Endura Volta Selective Tungsten CVD tool takes one to two months to start up, including facilities work, such as move-in, installation, and qualification. As is the case of ASML’s EUV scanners and Applied Material’s advanced tools, the company sends in a team to install, startup, and qualify customers’ processes.
To date, Applied Materials has sold more than 20 Endura Volta Selective W CVD system and all of them are currently used to selectively deposit tungsten on wafers processed using EUV-enhanced nodes. To that end, it impossible to quantify performance or power advantages brought by the Applied Materials tool since all the advantages of EUV fabrication technologies come in a package. Meanwhile, considering how important it is to minimize resistance at transistor contacts, it is safe to say that the selective tungsten fill process plays an important role.
Applied Materials positions the Endura Volta Selective W CVD system primarily for EUV-based nodes and since the machine is already in use, semiconductor makers will expand its usage as they expand usage of EUV lithography. Meanwhile, the company says that some of its customers are exploring ways to use the selective tungsten bottom-up gapfill process to increase performance of their current DUV-only nodes. As a result, the new tool can extend life of proven process technologies for some chipmakers.
“We have some customers who have expressed interest [applying selective tungsten deposition process to non-EUV nodes],” said Chen. “The amount of impact will not be as substantial as what you will achieve at 7 nm and beyond because you [already] have more room within that via. So, the impact of removing those liner/barrier and nucleation layers is not as significant, but you will still see a boost in performance.”
Further tungsten scaling
In the coming years foundries and ODMs will shrink transistors further and will adopt new transistor structures to scale performance, power, and area. Increasing the volume of tungsten conductors within a transistor contact (courtesy of selective tungsten deposition) lowers resistance and solves performance and power scalability challenges for years to come. As a result, switching to a new transistor contact conductor material, such as cobalt, may not be needed for a while.
“Cobalt is superior to conventionally processed tungsten (with a liner/nucleation layer) as a result of its ability to (i) work with a thinner liner, (ii) improved gap fill in small features due to its ability to reflow, (iii) lower resistance at these dimensions,” a spokesperson for Applied Materials explained.
Applied Materials says that selective tungsten deposition enables lower resistance at the contact when compared to conventionally-grown cobalt-based contacts, which use liner/barrier. To that end, transistor contacts grown using selective tungsten deposition process is a better choice than cobalt-based transistor contacts formed using conventional CVD.
“Selective tungsten is a complete rethink of how metallization is done,” the specialist from Applied Materials said. “There is no liner at all, and no nucleation layer, both of which handicap tungsten, and since it is grown bottom up, no seam (in the center as the material grows and converges from the sides). It turns out selective tungsten done as we do it [has] lower resistance than liner + CVD cobalt.”
As transistors shrink further and adopt new gate-all-around FET structures — enabled by nanowires, nanosheets, or nanoribbons — in the coming years, their contacts will shrink too. Perhaps, to a point when conventional chemical vapor deposition stops being viable. At that point, usage of selective deposition will be inevitable.
Meanwhile, cobalt contacts with liners formed using conventional CVD make a lot of sense as the first level contacts to the silicon source drain because cobalt is less sensitive to substrate materials.
“Liner + CVD Co turns out to be a very forgiving technology (less sensitive to substrate material) and will likely continue to be a better choice for the first level contact to the silicon source drain, while selective tungsten is a superior choice for the second level contact being made to the metal layer,” said Applied Materials.
Applied Materials’ selective tungsten deposition process as well as the Endura Volta Selective W CVD system were designed to substantially reduce resistance of transistor contacts and unlock performance potential of modern process technologies most of which use EUV lithography. The new process replaces traditional chemical vapor deposition used to grow transistor contacts and to some degree simplifies formation of conductors.
The Santa Clara, California-based company says that selective tungsten deposition allows to form transistor contacts that have a lower resistance when compared to cobalt-based contacts that are grown using conventional CVD process. As a result, the new selective deposition technology significantly prolongs life of tungsten as the preferred material for transistor contacts.
At present the new tool is used by leading chipmakers to produce chips using its 7 nm and newer EUV-enhanced nodes. Leading foundries started to process wafers using its EUV-based technologies well over a year ago and since then have processed hundreds of thousands of wafers, Applied’s new tool probably performs just as planned. To a large degree, the new system is one of the key enablers for EUV process technologies.
Some chipmakers who have not adopted 7 nm or more advanced manufacturing technologies are also exploring selective tungsten deposition process as an instrument to enhance performance of their nodes that use DUV lithography.
Engineers at Applied Materials believe that as transistors and their contacts shrink further in the GAAFET era, it will simply be impossible to produce them without using selective processes, so demand for the Endura Volta Selective W CVD tools will be strong for years.
Another interesting aspect about Applied’s Endura Volta Selective W CVD instrument is that it is made in the USA and therefore it is subject to export regulations by the U.S. Department of Commerce. To that end, it remains to be seen whether the new tool can be exported to Applied Materials’ customers in China.