Headstart over TSMC could give Samsung a leg-up in the post-FinFET era
Samsung’s foundry division offered an update to its process technology roadmap Tuesday, including the first process design kit for its forthcoming 3-nm gate-all-around (GAA) technology. Company executives also provided some details about advanced 3D packaging technologies and introduced a new cloud-based design environment.
Samsung plans to begin risk production of one of two 3-nm GAA processes it plans to offer by the second half of next year, with mass production expected in 2021. The company plans to begin risk production of the next 3nm GAA process in 2021, with mass production expected in 2022.
Last month, Samsung began volume production on its 7-nm FinFET process, the first to make use of next-generation extreme ultraviolet (EUV) lithography. While the company plans to roll out derivative 6-, 5- and 4-nm processes with FinFETs over the next two to three years, Samsung considers 3-nm to be its next major process technology node and the first that will use GAA three-dimensional multibridge-channel FETs, which feature gate material surrounding the channel region on all sides.
Voltage scaling of FinFET technology runs out of steam at 0.75V at the 10nm node. Samsung is implementing its GAA technology — which utilizes nanosheets as opposed to nanowires enabling greater current per stack — in order to reduce the operating voltage to 0.7V, said Yongjoo Jeon a principal engineer with Samsung’s foundry marketing team. Conventional GAA with nanowires requires a larger number of stacks due to its small effective channel width.
Samsung said it released its first process design kit (PDK) — version 0.1 — for its initial 3-nm GAA process last month.
“As far as I know, we are the only company that has a plan for putting gate-all-around in production,” Jeon said.
Samsung has about a one-year lead in GAA over TSMC, thanks to its heavy investment in R&D on advanced materials, including graphene, said Handel Jones, CEO of International Business Strategies. “Samsung is in a leadership position in 3-nm GAA and the key advantage is due to internal access to the materials for nanosheet structures,” Jones said.
Samsung said it recently taped out a test vehicle for first 3-nm GAA process, known as 3-nm GAE, which offers a 45% reduction in chip area, 50% lower power consumption or 35% higher performance compared to its 7nm process. Executives expect the process to be popular for compute-intensive applications, including mobile, network, automotive, AI and IoT.
“GAA will support analog functionality as well as digital, which gives it an advantage over FinFETs,” Jones said. “GAA will consequently have long lifetime and with multiple versions in device structures even though lithography does not shrink.”
Samsung, which officially spun out its foundry business from its System LSI business into its own unit in 2017, is currently the No. 2 ranked foundry player with about $10 billion in foundry sales last year. It trails TSMC — which had 2018 sales of about $33 billion — by a wide margin.
According to Ryan Lee, vice president of foundry marketing at Samsung, the company has roughly doubled its customer base since the time of the spin out. Samsung expects to grow foundry sales faster than TSMC going forward, Lee said.
Putting 3-nm in volume production in 2020 would seem to give Samsung a leg up on competitors including TSMC, Globalfoundries and Intel — although process technology comparisons based on the transistor node are not apples to apples.
“Gate-length has lost its meaning as a descriptor of semiconductor fabrication processes, but Samsung’s 3-nm technology is significant for its first industry use of gate-all-around transistors,” said Mike Demler, a senior analyst at the Linley Group. “TSMC hasn’t publicly disclosed its roadmap past 5nm, but if Samsung hits its target of mass production in 2021, it could surge ahead for the post-FinFET generation.”
Still, Demler said, generation-to-generation process technology improvements in process technology continue to decline. Compared to its 7-nm technology, Samsung 5-nm process — set for mass production in the second half of next year — improves logic density by just 25%, he said. The 3-nm GAA process adds just 20% improvement on top of that, he said.
“The performance improvements [with 3-nm GAA] are a bit better than the 7-nm to 5-nm gains, but the power improvement is the same,” Demler said.
At the same time its is ramping up advanced process technologies, Samsung is also expanding its capacity for more mature process nodes at 20-nm and above. Lee said Samsung would expand its 200-mm wafer capacity from about 2.5 million wafers per year to about 3.5 million wafers per year in the next two years.
The cloud-based design environment, known as the Samsung Advanced Foundry Ecosystem (SAFE) Cloud program, features the collaboration of cloud-service providers such as Amazon Web Services (AWS) and Microsoft Azure, as well as leading EDA vendors such as Synopsys and Cadence. It is intended to provide customers with flexibility and reduce their infrastructure requirements, according to Samsung.