Samsung Foundry Promises Gate All-Around in 2022

Article By : Kevin Krewell

Samsung plans to leapfrog TSMC and Intel to become the first major foundry to get a version of gate all-around transistors in production.

Samsung Foundry recently held its Foundry Forum where it revealed some details of its semiconductor process roadmaps and fab expansion. Samsung is being most aggressive pursuing the next generation of transistor technology, with plans to reach mass production ahead of TSMC and Intel. Samsung’s 3-nanometer process will use the gate-all-around (GAA) transistor structure, which the foundry calls MBCFET (Multi-bridge channel FET) and will be in production first half of 2022.  TSMC will wait another generation until its N2 process to deliver GAA some time in 2023.

Intel will bring its version of GAA, called RibbonFET, into production in its 20A process, likely in mid-2024. While Samsung is being the most aggressive on this technology, TSMC will deliver its 3-nanometer node earlier in 2022 using the more conservative approach by extending the life of FinFET designs. Intel will also use its “Enhanced SuperFin” transistors for the Intel 4 node in 2022, and the Intel 3 node in 2023. All these new nodes, both FinFET and GAA, are using extreme ultraviolet (EUV) lithography. It should also be noted, that neither Samsung nor TSMC has decided to follow Intel and rescale the node names from nanometers to Angstroms, at least not yet.

Samsung’s version of the gate all-around (GAA) transistor is the multi-bridge field effect transistor. The company said that designers can balance power against performance by by modulating the device channel width. (Source: Samsung Foundry)

The first Samsung GAA node is 3GAE, in mass production by end of 2022, followed by the 3GAP node by the end of 2023. The 2GAP node will not make it into mass production until 2025. Samsung executives said at a press conference before the Forum that its new MBCFET technology is more expensive to manufacture, but it will “strive” to continue to lower the cost per transistor. The 3nm MBCFET node will allow up to 35% decrease in area, 30% higher performance or 50% lower power consumption compared to its 5nm process.

It should be noted, that despite not have production fabs itself, IBM is deeply involved with the advanced GAA process development at the company’s semiconductor development efforts based at its research lab located at the Albany Nanotech Complex in Albany, NY. Samsung is part of that program and, just this year, IBM added Intel to the program. Which might explain why both IBM and Intel made appearances during the Samsung event. Samsung is also the foundry partner for IBM’s latest Power 10 and Telum Z Processors.

But why is GAA so important you might ask? With GAA, there is more control over the gate. While the finFET had discrete number of fins and limited control over height, GAA allows more control over the width of the nanosheet and the stacking, and allows better electrostatic control of the gate, and that allows smaller gates.

One effect of this improved control is the ability to lower supply voltages, which reduces transistor power. While early GAA prototypes used nanowires, all production GAA transistors use “nanosheets” that can be constructed with variable widths. The variable widths allow finer-grained control over the transistor size and drive capability, compared with FinFET.

All is not lost for the FinFET though. Samsung will continue to develop 14nm and 17nm FinFETs for specialty applications, such as RF, and has developed the 17nm node with 14nm front-end-of-line with a 28nm back-end-of-line to bridge the gap with 28nm planar transistors. Samsung’s 5nm node will also be qualified for automotive use.

New packaging technologies have become de rigueur for all the foundries as more chiplets, tiles, 2.5D and 3D options proliferate. Samsung is calling these packaging options “beyond Moore” for heterogeneous integration and will be offering 3D IC, microbumps, hybrid bonding, and “3.5D” options to keep pace with Intel and TSMC. TSMC has a strong roadmap and experience in packages with its CoWoS, InFO and SoIC technology and made packaging a major topic at its recent Technology Summit. Intel’s Foveros and EMIB technologies have likewise been touted as a differentiator.

New Fabs to the Rescue

Another key Samsung announcement is that it plans to expand its capacity by 3.2 times by 2026, including a new fab in the U.S. But Samsung would not provide a location, size, or timeline for the US fab, but does already have a fab (S2) in Austin, Texas. Samsung is also considering fab expansion for legacy nodes, which have been a major part of the recent chip shortages. TSMC has committed to new fab in Phoenix, Arizona for its N4 node and Intel has broken ground for a new advanced fab in Chandler, Arizona.

The foundry race between Samsung and TSMC has not slowed, and now Intel is entering the race as well. While Samsung may not be the first to deliver 3nm production volumes, the Samsung GAA transistor should have better performance and power characteristics. The challenge for Samsung is to maintain the lead after TSMC rolls out its N2 node and Intel’s 20A node in 2024.

This article was originally published on EE Times.

Kevin Krewell is Principal Analyst at Tirias Research. Before joining Tirias Research, he was a Senior Analyst at The Linley Group and a Senior Editor of Microprocessor Report. He spent nine years at MPR in a variety of roles, contributing numerous articles on mobile SoCs, PC processors, graphics processors, server processors, CPU IP cores, and related technology. For The Linley Group, he co-authored reports that analyzed market positioning and technical features of the various vendor products. He has more than 25 years of industry experience in both engineering and marketing positions. Before joining The Linley Group, Kevin was Director of Strategic Marketing at Nvidia and Director of Technical Marketing at Raza Microelectronics (now part of Broadcom). He spent more than a decade at AMD in various roles, including technical marketing manager and field application engineer. He also understands the needs of engineers, having spent 10 years in product design at several smaller companies. He earned a BS in electrical engineering from Manhattan College. He also holds an MBA from Adelphi University and is a member of the IEEE as well as a member of the Microprocessor Oral History SIG for the Computer History Museum.

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