S-MOS Cell Technology Improves Efficiency of SiC MOSFETs

Article By : Maurizio Di Paolo Emilio

Startup rqSemi has unveiled a singular point source MOS cell concept suitable for power MOS-based devices.

A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS-based devices was presented by the startup company mqSemi. The S-MOS concept has been adapted and implemented on a 1200V SiC MOSFET structure by means of 3D-TCAD simulations using Silvaco Victory Process and Device Software. A full set of static and dynamic results has been presented for comparing the S-MOS with reference SiC MOSFET 2D structures employing Planar and Trench MOS cell designs.

The performance of silicon-based power devices, such as power MOSFETs and insulated gate bipolar transistors (IGBTs), has been greatly improved over the years using MOS cell process and design platforms. Both these devices have been based either on planar or trench MOS cells, arranged in cellular or linear layout designs.

The results achieved on silicon-based MOS devices can be exploited for the development of SiC power MOSFETs, where high cell packing density is an essential requirement. In order to improve the static and dynamic characteristics of the device, over the past few years, advanced 3D design concepts have been proposed. These 3D structures are similar to the low voltage FinFET cell structure, where multi-dimensional channel width is arranged in order to increase the cell density and reduce the on-state resistance RDS(ON).

One of the advantages of adopting SiC as a power device material is the ability to use many of the well-known silicon device principles and processing methods. Basic device designs, such as vertical Schottky diodes or vertical power MOSFETs (after certain diversions via JFETs and BJTs as alternate topologies) are among them. As a result, many of the processes for ensuring the long-term stability of silicon devices may be applied to SiC. However, a more thorough examination revealed that SiC-based devices require extra and distinct reliability tests than Si-based devices, including the material with its specific properties and defects, the larger bandgap, and higher electrical fields — especially in the junction termination region, the operation with higher temperatures and switching frequencies.

S-MOS cell concept

Aligned with this three-dimensional structure trend is the Singular Point Source MOS cell concept (also called S-MOS) developed by mqSemi. Founded by Munaf Rahimo and Iulian Nistor with headquarters in Switzerland, mqSemi develops advanced power semiconductor concepts addressing next-generation power electronics systems for applications such as e-mobility, automotive, and renewables. With over 20 patents filed in the past two years, mqSemi has done a lot of simulation and is now ready for the prototyping phase. The many years of experience and knowledge acquired by the mqSemi team on IGBTs, helped a lot in addressing the critical issues of silicon carbide MOSFETs such as lowering the losses, providing robust short circuit mode, and blocking behavior, gate drive control, and high-frequency oscillations.

“We believe that for a sustainable world we will need applications based on efficient, compact, reliable, and cost-effective power semiconductor devices, that are technology-forward and innovation-centered,” said mqSemi’s Rahimo and Nistor.

S-MOS benefits are twofold: on one side it carefully defines the total channel width using a unique method, also known as channel area; on the other, it enables higher MOS cell packing densities. Moreover, the S-MOS concept can be implemented on both MOSFETs and IGBTs, improving switching performance while achieving higher efficiency and lower overall losses.

An S-MOS cell differs from both a standard Planar cell and a Trench MOS cell in how the total channel width per device area (the Wch parameter) is devised. As shown in Figure 1a and Figure 1b, respectively, the channel width Wch for planar or trench MOS cell is defined as the total peripheral distance around the N++ source, and it also depends on the geometrical shape of the MOS cells arrangement (linear or cellular layout design). The S-MOS single cell channel width Wch, shown in Fig. 1c, is defined by a small-scale dimension of the N++ source and PChannel junction WPNJ length. By positioning this small geometrical feature on a trench side-wall, a predetermined unit channel length Wchn is provided. For the S-MOS, the N++ and PChannel profiles are similar to those of a planar cell, but are positioned on a trench sidewall. The total channel width is therefore dependent on the total number of gated trench side-walls per chip. As shown at the bottom of Figure 1c (red dashed line), the shape of the N++/PChannel junction can be approximated to a quarter of a circle, reaching for Wchn a size around 150-300 nm for a single trench side-wall. The total Wch for a given chip area can be obtained as the sum of all Wchn on all trench sidewalls.

MOS cell concepts. (Image source: mqSemi)

The S-MOS concept has been demonstrated by means of 2D and 3D TCAD simulations conducted on 1200V SiC MOSFETs, including the S-MOS and references planar and trench structures.

“During the simulation, we found a very special feature, that we were not expecting, on the sidewall of a trench, where we could get the so-called channel width which defines the total channel density which was something based on a diffusion profile,” stated mqSemi.

The simulation was performed on a 1200V SiC MOSFET because the static losses, measured by Rds(on), are not difficult to assess. The same technology can be applied to different voltage classes, as well. Static and mixed-mode inductive load dynamic simulations were carried out for all device structures (S-MOS, Trench and 2D Planar), which were scaled for a total active area of 1cm2. The output voltage-current characteristics obtained with the simulation are shown in Figure 2; the upper image refers to a voltage range up to 600V, while the lower image is a zoom-in up to 1V at Vgs=15V and 150°C. The S-MOS concept has provided low Rds(on) levels (around 3 mΩ-cmat 150°C), similar to trench cells. However, as shown in Figure 2, the S-MOS provides also a flat saturation current compared to the other referenced models.

1.2kV SiC MOSFET output curves, Vgs=15V, 150°C (Image source: mqSemi)

“What we found is that we had better switching controllability, and that was the whole idea of going in the third dimension. We obtained a much-reduced switching loss compared to the trench cell, and there was much more design freedom for us to further optimize it and obtain even higher cell densities,” added mqSemi.

The short circuit current was simulated at 150°C for all devices, showing how S-MOS exhibits less short channel effects and improved trade-off between conduction losses and short circuit performance. Even though the S-MOS concept still needs further design optimization, the performance demonstrated is very promising, and at mqSemi, they are ready for the next stage, which is prototyping.

This article was originally published on EE Times.

Maurizio Di Paolo Emilio holds a Ph.D. in Physics and is a telecommunication engineer and journalist. He has worked on various international projects in the field of gravitational wave research. He collaborates with research institutions to design data acquisition and control systems for space applications. He is the author of several books published by Springer, as well as numerous scientific and technical publications on electronics design.

 

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