RISC-V Adoption to get a Boost from FreeStart

Article By : Nitin Dahad

The company has implemented a program that enables designers to try RISC-V for free using its N22 core, with no upfront IP licensing fees

Zurich – What’s clear from listening to the community here at the RISC-V Workshop at ETH in Zurich is that the architecture is still in its infancy and a handful of companies are trying very hard to boost adoption, and convince developers of the benefits of the technology.

It’s no surprise then to see the launch of a program encouraging designers to try RISC-V for free, in other words no license fee.  Andes Technology Corporation announced its RISC-V FreeStart program, which chief technical officer Charlie Su said aims to help ‘take RISC-V mainstream’.  The program offers an easy way to build a system-on-chip (SoC) foundation on its commercial-grade RISC-V CPU core N22, available for free download. The AndesCore N22 is an entry-level, low-power RISC-V CPU which delivers a performance of 3.95 Coremark/MHz, which Andes says is the highest in its class. Its configurable features include multiplier, interrupt controller, local memory, instruction cache and debug support. With the RISC-V FreeStart program, SoC engineers can begin designing a RISC-V based SoC without having to budget for CPU IP costs upfront.

Andes Technology president, Frankwell Jyh-Ming Lin, said designers are looking for small, efficient, commercial RISC-V cores to construct their creative SoCs. “Unlike open source RISC-V CPUs which are with limited features and lack of documents, and need to be verified by SoC designers first, users of the commercial-grade N22 can skip this time-consuming task which adds nothing to the value of their final SoC and instead spend their precious design resources on their true value added.”

CTO Su said the N22 CPU is a small, 2-stage pipeline 32-bit RV32I/EMAC RISC-V CPU core, with 16 or 32 general purpose registers, and supports several configurable features such as StackSafe for hardware stack protection, PowerBrake for efficient power management, CoDense for code size reduction on top of RISC-V C extension, and local memory and instruction cache for performance boost. 

Andes Tech

A pre-integrated N22-based  platform for Andes Technology’s new FreeStart program. (Source: Andes Technology).

While the program is free, it also provides designers the option of one-year support at a cost of $20k, and a pre-integrated AHB platform with commonly used peripheral IP blocks. In addition, RISC-V FreeStart also uses the free download AndeSight IDE, a professional software development environment with over 15,000 worldwide installations. Under the RISC-V FreeStart program, Andes hopes anyone from industrial professionals to school students will view and sign the online license agreement and download the N22 processor for evaluation. It also provides a migration path to mass production to enable commercial use, where customers pay royalties.

We had mentioned this new program to Arm – currently the dominant player in the RISC processor space – who were also in attendance at the Zurich workshop, and they were keen for us to point out it also provides a free program for its M-class processor cores, called DesignStart. Tim Whitfield, Arm’s VP of strategy for embedded and automotive told EE Times here, “I think this is quite clear that access is free and for Cortex-M0/3, the only fee is through a success-based royalty model.”

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