Researchers solve CNT semicon yield, density issues

Article By : EE Times Asia

A Korean team has used a high-yield carbon nanotube process to pack 600 CNTs/μm, paving the way for next-gen wafers to be fabricated without changing equipment.

Most electronic equipment and devices are still using silicon semiconductors as it is difficult to fabricate highly purified and densely packed semiconductors with carbon nanotubes(CNTs). A research team from the School of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) led by Professor Yang-Kyu Choi, in collaboration with Professor Sung-Jin Choi of Kookmin University, is set to change that.

 
[CNT semiconductor fig1 (cr)]
Figure 1: 3D rendering of the CNT Electronic Device and its Scanning Electron Microscope (SEM) image.
 

The scientists have developed a semiconductor that features high-current density with a width less than 50μm. They used a 3D fin-gate to vapour-deposit CNTs on its top. The 3D fin structure enabled them to pack 600 CNTs/μm. This structure can have 20 times more nanotubes than a 2D structure, which can only vapour-deposit 30 in the same 1μm width.

CNT-based semiconductors are expected to be five times faster than silicon-based devices and will require five times less power during operation. In addition, the research team has used semi-conductive CNTs having a purity rating higher than 99.9% from a previous study to obtain a high yield semiconductor.

 
[CNT semiconductor fig2 (cr)]
Figure 2: 3D transistor device on an 8-inch base and the SEM image of its cross section.
 

Furthermore, the new semiconductor can be made by or will be compatible with the equipment for producing silicon-based semiconductors, so there will be no additional costs.

Researcher Lee said, “As a next-generation semiconductor, the carbon nanotube semiconductor will have better performance, and its effectiveness will be higher. Hopefully, the new semiconductor will replace the silicon-based semiconductors in ten years.”

Dong Il Lee, a postdoctoral researcher at KAIST’s Electrical Engineering School, first authored this study entitled “Three-Dimensional Fin-Structured Semiconducting Carbon Nanotube Network Transistor.”

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