Renesas Electronics Corp.'s low-jitter 9SQ440 clock generator IC is designed for next-generation Intel platforms used in high-performance computing and data center applications.
Renesas Electronics Corp. announced the availability of the low-jitter 9SQ440 clock generator IC designed for next-generation Intel platforms used in high-performance computing and data center applications. The latest in a long line of industrial PCIe devices, Renesas’ 9SQ440 is a clock generator designed to follow Intel’s CK440Q specification and future Intel Xeon processor requirements. The 9SQ440 addresses the challenges of PCIe Gen5 design.
As clock generators are at the heart of data center timing, the advent of increasingly complex systems requires significant design flexibility, said Yimu Guo, product manager of Cloud and Compute Timing products, at Renesas, in an interview with EE Times Europe.
Designers can combine Renesas’ new portfolio member with other solutions such as PCIe Gen5 clock buffers and infrastructure and smart power stage (SPS) devices in data centers.
Jitter is the random, uncontrolled, unwanted variation of parameters such as, for example, amplitude, frequency and phase of a signal. Therefore, it is easy to understand the negative consequences in the treatment of signals, especially in high and very high-frequency communications. Jitter can worsen your bit error rate (BER), both in the acquisition and signal processing phases. Since there are no “stable” parameters in nature, any digital signal is affected by jitter (just as any analog signal is affected by noise). So it’s important to know your design margin how to mitigate around these issues.
“Jitter is extremely important; it is one of the most important factors. The higher the speed, the lower the jitter requirement. You would want your clocks to be as clean as possible so they don’t eat up the channel budget. In today’s 100-fsec RMS world, the challenge is to provide very low jitter products, delivered to customers in hand even before the system specification is fully finalized. This is not an easy task considering the power budget and further feature integrations you would have to consider here,” said Guo.
A timing system can be represented by phase-lock looping, crystal oscillation, clock buffering, digital synchronization, including software. They are based on two main assumptions: All signals are digital and all components share a common, discrete concept of time: It is identified by the clock signal common to the circuit.
Clock generator trends and challenges
Clock generators are the heart of the system. In terms clock and timing, the challenges are scaling and syncing. “The number of clocks is definitely growing with peripherals like storage devices and accelerator cards,” said Guo. He added, “at the same time, with systems becoming disaggregated over time, they need to be more aware of each other. With more and more computing power being pushed to the edge, we’re seeing synchronization requirements like PTP/IEEE1588, which is traditionally only seen in the telecom world, now going into the compute world. This requires a certain set of both hardware and software to solve; replicating the telecom solution will not work. It will require a different clocking mindset to be scalable for the modern compute world.”
The 9SQ440 serves as a centralized clock generator for the server CPU and PCIe clocks. It features a total of 20 differential outputs, and less than 50fs RMS of common PCIe Gen5 clock phase jitter. It supports multiple CPU socket topologies, ranging from a single standalone socket to modular multi-socket approaches.
With timing devices incorporating more and more LDOs internally, they’re subject to noises. “For one, you have to arrange your filters and everything to ensure your clocks are outputting clean clocks,” said Guo.
Another key challenge is that, as the system powering sequence becomes increasingly difficult to control, clocks won’t always be powered at the most desired moment. “A good example of addressing this challenge is our Flexible Power Sequencing, which ensures well-defined behavior under various power-up scenarios – whether power applies to the clock before, or after input signal applies, it’ll always function right. This means no leakage when applying a clock when VDD is down, nor any glitches/noisy-outputs when VDD is up before any inputs,” commented Guo.
The jitter performance of the reference clock is an important consideration. The higher data throughput of PCIe Gen 5 requires a reference clock with low jitter. The increased throughput with PCIe Gen 5 is particularly beneficial for various bandwidth-intensive applications, such as servers, high-end storage subsystems, and accelerators. Using PCIe 5.0, various next-generation platforms will also support CXL and Gen-Z protocols specifically designed to connect CPUs with various accelerators and maintain memory and cache coherency at low latencies.
The use of spread spectrum clocking is an important consideration when selecting a PCIe clock source to offer a lower radiated electromagnetic interference (EMI) that is generated by high-speed clock and datapath signals.