PCIe 7.0 To Double Data Rate – Again

Article By : Gary Hilson

PCI–SIG sets 2025 deadline for PCIe 7.0, commits to bandwidth doubling, backwards compatibility.

The sixth iteration of the Peripheral Component Interconnect (PCIe) specification only came out at the beginning of the year, but the organization responsible for shepherding it is already looking ahead to PCIe 7.0.

During the PCI–SIG Developers Conference 2022, the PCI Special Interest Group (SIG) announced it has committed to releasing PCIe 7.0 in 2025. PCI-SIG technical workgroups are getting to work now, said Al Yanes, president and chairperson at PCI-SIG, with the aim of doubling the data rate to 128 GT/s and up to 512 GB/s bi–directionally via x16 configuration.

The PCIe specification has doubled the I/O bandwidth every three years and that remains the goal for PCIe 7.0 to be delivered in 2025 (Source: PC–SIG) (Click image to enlarge)

PCI–SIG’s seventh iteration of PCIe aims to continue to deliver low–latency and high–reliability targets, improve power efficiency, and continue to maintain backwards compatibility with all previous generations. The next generation of the spec will use Pulse Amplitude Modulation with 4 levels (PAM4) signaling and focus on channel parameters and reach.

Yanes said PCI–SIG’s confidence in its ability to deliver on these goals is based on its success with PCIe 6.0. It moved from NRZ to PAM4 signaling and flow control unit-based encoding that supports the PAM4 modulation and works in conjunction with newly added Forward Error Correction and the Cyclic Redundancy Check to enable the bandwidth doubling.

“It was a revolutionary transition for us to switch from NRZ Z to PAM4,” he said. These capabilities were added without sacrificing latency or backwards compatibility.

The goals laid out for PCIe 7.0 reflect the requirements of the emerging applications the PCI–SIG is targeting, such as 800 G Ethernet, AI and machine learning, cloud computing, and even quantum computing, as well as data–intensive uses cases such as hyperscale data centers, high–performance computing, and military and aerospace applications.

“Obviously not everybody needs the PCIe 7.0 or PCIe 6.0 bandwidth,” Yanes said. “The folks that do the HPC, the artificial intelligence and machine learning are are the ones that are going be adopting the higher speeds to meet bandwidth goals.”

If that weren’t enough, the PCI–SIG will be exploring automotive opportunities, which were already on the horizon with PCIe 6.0. But the road ahead for PCIe 7.0 implementation in vehicles isn’t altogether clear, Yanes noted. “We’re focusing heavily trying to get inroads there.”

A working group is in in place to focus on the automotive aspect, with the number of sensors generating data within a vehicle being a major consideration. With most cars hitting Level 2.5 of autonomy, there are about 30 to 50 sensors supporting vehicle functions and driving bandwidth requirements.

As it stands, not even PCI 6.0 has been adopted into automotive applications due to a lack of certification for the reliability automakers require, such as Automotive Safety Integrity Level (ASIL) D certified under ISO 26262. It’s one of the most stringent safety integrity levels for automotive safety. It takes about year to obtain, Yanes explained.

Micron Technology just announced its LPDDR5 DRAM memory is now ASIL D certified in anticipation of Level 5 autonomy, which is further down the road than initially expected.

The PCIe bus standard has become foundational for many other technologies and specifications that facilitate data movement. Both the relatively mature Non-Volatile Memory Express protocol as well as the fledgling, yet rapidly evolving, Compute Express Link are leveraging the ubiquity of PCIe.

This article was originally published on EE Times.

Gary Hilson is a general contributing editor with a focus on memory and flash technologies for EE Times.

 

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