The features of the latest memory ICs are not just smaller, they are physically more complicated. Advanced memory manufacturing utilizes complex design features that require precise pattern alignment to achieve high yielding, reliable devices
IC fabrication involves the addition and removal of many patterned layers of different materials to create a functional semiconductor device. During the manufacturing process, it is critical that each patterned layer is precisely aligned to the previous layer to ensure electrical contact and produce a functioning device.
Overlay metrology is used by fabs to measure and control this pattern-pattern alignment during production. Overlay error is typically measured on targets – specialized pattern structures in discrete locations across the exposure field. These target measurements must correlate with the overlay error happening on actual device pattern.
Advanced memory manufacturing utilizes complex, high aspect ratio design features that require precise pattern alignment to achieve high yielding, reliable devices. 3D NAND devices use >100 layer pairs, double stack construction, and materials such as thick hard masks that introduce overlay measurability challenges related to high topography, opaque materials, and wafer stress. DRAM manufacturing continues to move to smaller design nodes, resulting in more stringent overlay error specifications. This memory device complexity is driving the need for novel overlay metrology methods that achieve the needed accuracy and precision for overlay control in high volume manufacturing.
The design of the overlay target is critical to enabling accurate and robust overlay metrology, particularly for complex 3D NAND and DRAM devices. New overlay targets, such as the robust AIM (rAIM) imaging-based overlay (IBO) target, are designed to provide improved robustness and process resilience. The rAIM target takes advantage of the Moiré effect and its double scattering interference pattern, which is implemented using a smaller pitch as compared to standard AIM targets. This smaller pitch is more representative of the smaller design rules used for advanced devices. Overlay results on production wafers using the rAIM target show an improvement of 15% for correlation of IBO ADI (after-develop inspection) to SEM AEI (after-etch inspection) measurements, while also showing a residuals reduction of 10% and total measurement uncertainty (TMU) reduction of 25%.
Innovative target designs are also needed for advanced DRAM manufacturing, where the overlay error budget is approaching the sub-2 nm threshold. To obtain the resolution required to print these complex DRAM patterns, scanners use tilted extreme dipole illumination. Conventional overlay targets, consisting of horizontal or vertical lines, do not provide the accuracy required in overlay device tracking and do not fully correlate to tilted device structures. To address this pattern discrepancy, the Diagonal AIM (DAIM) overlay target uses tilted patterns, which are more representative of the device being manufactured. The DAIM overlay mark demonstrates significant improvements in device overlay tracking for complex DRAM products.
In addition to new overlay target designs, advanced memory manufacturers are seeking IBO measurement solutions that address challenges related to accuracy, residuals reduction, measurability, and resilience to process variation. For example, most critical 3D NAND process layers have high topography and can have large process variations. To achieve the best overlay performance, measurements need to be taken with different optical setup configurations depending on the characteristics of the layer being measured. The wave tuning (WT) capability of the Archer 750 overlay metrology systems allows use of a custom measurement filter comprised of the best wavelength and measurement bandwidth for the layer being measured. Wave tuning, along with other setup configurations, such as variable NA, polarization and focus optimization, significantly improve measurement conditions and overall metrology performance. Overlay measurement performance is further improved through the integration of machine learning algorithms that can help improve calibrated overlay accuracy on both DRAM and 3D NAND layers.
Advanced DRAM and 3D NAND memory devices – with their complex design features, high aspect ratio structures, opaque materials, and thick film stacks that produce high wafer stress – introduce a new set of challenges to overlay metrology systems. However, these challenges can be addressed by innovative new overlay target designs, customizable measurement configurations and the implementation of machine learning algorithms that together improve overlay accuracy, precision, and process resilience.
— Efi Megged, director of product marketing at KLA, and Joe Clinton, technical communication specialist at KLA