Edge placement error has emerged as a new challenge to good semiconductor yields, says an expert from Applied Materials who gives guidance for dealing with it.
For past semiconductor technology nodes, the industry took for granted that the edges of features within a chip could, for practical purposes, be considered straight and reasonably well aligned to other feature edges from layer to layer. But as dimensions shrink, the allowable tolerance for edge placement error (EPE), which refers to the vertical misalignment of features, has also shrunk and those past assumptions are no longer valid.
In advanced multi-layer chip designs and with chips getting smaller for emerging packaging schemes, EPE poses an unacceptable limitation on yield, and traditional methods of aligning feature edges are inadequate. This difficulty affects (intermediate) edges defined by photolithography, deposition and etch processes that produce a single final edge, as well as alignment between layers–for example, between metal 1, metal 2 and the vias that connect them. Even the smoothness of a final edge is now a potential error issue impacting alignment.
As error margins tighten, tiny incremental process variations can add up to a major problem. These newly significant variations must be measured during the ramp-up of a process or a particular product–and possibly even as part of ongoing process monitoring. This creates a special challenge for metrology, especially when aligning multiple layers, some of which will be deeper into the silicon stack.
An artist's rendering of the EPE issue. (Source: Applied Materials)
Errors within a layer can be caused by one or more of the following:
Lithography: Mask registration may be off, either by linear translation or by rotation. This could be caused by the layout or by the equipment. Even when layout is the issue, however, it’s too expensive to fully optimize masks through iteration, so much of the corrective action falls to manufacturing to address.
Hardmask etch: Poor cross-wafer uniformity may place edges properly on some die while misplacing others–especially at the wafer edge. Additionally, feature sizes can affect local etch results. This can actually be leveraged to help correct errors originating in lithography, but help from etch engineers is typically needed.
Material deposition: Selection of a substandard film for an application might mean compromising uniformity of the material composition, poor etch selectivity and possible mechanical stresses. A better-quality material may pay for itself through improved die yield.
These combined issues make it necessary to optimize processes and layout to the extent practical to minimize EPE. However, when aligning multiple layers, better yields may be achieved by optimizing the layers of the stack together rather than focusing on and optimizing each individual layer one at a time.
When developing a challenging new process or taking an aggressive new design into production on an existing process, controlling EPE requires metrology technology that can “see” and measure the location of the device feature relative to the layers above and below. That means seeing multiple layers at once, but the buried lower layers won’t be visible with conventional e-beam or optical technologies; optical methods average defect signatures from multiple features so they actually hide individual errors.
High-energy electrons can help. An e-beam with a high target impact energy can penetrate deep into the processed wafer, providing visibility to the buried layers. A 10x improvement in the high-energy efficiency of the electrons also is required to collect data across many die on different parts of a wafer as well as across multiple wafers. Once that huge data set is in place, it becomes possible to search for signatures that will point to edge issues.
With the leading-edge nodes in use or in development–from 10nm down–EPE must be accounted for when readying those processes for high-volume production. Initial focus should be on the connection between layers. Optimizing across those layers can be more effective than optimizing each individual layer by itself and, at the very least, addressing the problem using high-energy e-beam technology may be more economical and practical than the traditional approaches.
–Regina Freed is managing director of patterning technology at Applied Materials and has more than 20 years of experience in the semiconductor industry, managing lithography, metrology, and defect inspection for logic and memory processes.