Optimizing Package System Integration Maximizes System Performance

Article By : Ravi Mahajan

Closer collaborations between package and system designers to optimize package system integration will help maximize system performance.

Announcements involving advanced packaging architectures for semiconductor devices have multiplied in recent years. These architectures offer product designers tremendous flexibility and enable significant performance enhancements by heterogeneously integrating different IP elements — optimized on different silicon processes — on a single package.

Recent interest in advanced packaging is driven by the need for increased on-package bandwidth, the need to integrate diverse intellectual property from multiple foundries, and the need for improved yield resiliency. Organic packages are excellent mainstream platforms for heterogeneous integration, offering space transformation in compact form factors and increasingly power-efficient, high-bandwidth physical on-package interconnects (Figure 1).

The Intel Agilex FPGA provides an example of on-package heterogeneous
integration. (Source: Intel)
Figure 1: The Intel Agilex FPGA provides an example of on-package heterogeneous
integration. (Source: Intel)

One of the goals of advanced packaging is to develop increasingly dense lateral and vertical interconnects such that the die-to-die links created with these interconnects have minimal power loss and latency while ensuring signal integrity. Essentially, the focus is to create on-package interconnects that approach monolithic interconnect performance and to ensure that the composite device created on the package behaves as a virtual monolithic entity.

2D and 3D architectures

On-package interconnects and, more broadly, the package architectures based on those interconnects can be classified as 2D in the x-y plane of the package and 3D for vertical, stacked configurations (Figure 2).

The interconnect nomenclature for 2D and 3D architectures (Source: Electronics Packaging Society, IEEE)
Figure 2: The interconnect nomenclature for 2D and 3D architectures
(Source: Electronics Packaging Society, IEEE)

A 2D architecture is defined as an architecture in which two or more active silicon devices are placed side by side on a package and are interconnected on the package. If the interconnect has higher interconnect density than mainstream organic packages and that enhancement is accomplished using an organic medium, the resultant architecture is subcategorized as a 2D organic (2DO) architecture. Similarly, if the enhanced architecture uses an inorganic medium — a silicon, glass, or ceramic interposer or bridge — the architecture is subcategorized as a 2DS architecture.

A 3D architecture is defined as an architecture in which two or more active silicon devices are stacked and interconnected without the agency of the package. The phrase “interconnected without the agency of the package” in this definition simply means that the interconnects between the active silicon do not pass through the package, and hence, their design and performance do not directly depend on the package architecture.

Interconnect density

Physical interconnect density can be captured by two key metrics (Figure 3). Linear density represents the number of wires escaping the die edge for lateral die-to-die interconnects, and areal density characterizes the number of bumps used to form vertical connections.

Linear and areal interconnect density can be captured by these two key metrics. (Source: Intel)
Figure 3: Linear and areal interconnect density can be captured by these two key metrics. (Source: Intel)

Figure 4 and Figure 5 describe the envelopes for the linear and areal densities for different packaging technologies. As both figures indicate, a wide range of interconnect densities are possible with different interconnect architectures. In general, technologies that use silicon back-end wiring have the highest wiring densities because they offer thinner and more closely spaced wires (Figure 4).

Linear interconnect density envelopes for different advanced packaging.
Figure 4: This graph shows linear interconnect density envelopes for different advanced package architectures. (Source: Intel)

These technologies enable parallel, wide, and slow die-to-die links and require careful attention to the link design to address the signal-integrity issues associated with increased wiring densities. As the bump pitch shrinks, the areal bump density increases proportionally to the reciprocal of the square of the bump pitch (Figure 5).

Areal interconnect density as a
function of bump pitch and architecture. (Source: Intel)
Figure 5: This graph shows areal interconnect density as a
function of bump pitch and architecture. (Source: Intel)

A vast majority of the areal die-to-die and die-to-package interconnects today use solder to form the joints. As bump pitch shrinks, there will be a transition away from solder to using Cu-Cu interconnects (at ~20–25 µm) to enable continued interconnect density scaling. Hence, there is a focus in the industry to increase the technology envelope of Cu-Cu interconnects.

A common underlying reason for interconnect density scaling is the need to increase bandwidth for on-package die-to-die links. The rate of bandwidth scaling can be used to define an interconnect scaling roadmap. According to the Heterogeneous Integration Roadmap 2019 Edition, the interconnect technology scaling roadmap enables generational doubling of link bandwidth.

Figure 6 shows some examples of advanced packaging architectures for heterogeneous integration.

examples of advanced packaging architectures for heterogeneous integration
Figure 6: Some advanced package architectures offer increased partitioning opportunities and scaling in all three dimensions. (Source: Intel)

Collaboration between package and system designers

As advanced packaging technologies evolve, they will provide increased on-package performance through heterogeneous integration, which enables increasingly higher-performance systems. This system performance can be better realized by strengthening collaborative partnerships between package and system designers.

Here are some examples of how collaborative partnerships will help maximize system performance:

  • System board features, materials, and designs must evolve to support higher-speed and higher-bandwidth signaling. Package and system co-design approaches to create power-efficient, cost-optimized system links that maximize bandwidth will help maximize system performance.
  • It is anticipated that, in addition to electrical links, photonics and wireless links will be needed in the future to maximize reach and bandwidth. Developing and proliferating those signaling techniques will require collaborations to enable standardized, modular scalability.
  • A focus on developing an efficient system power delivery network will be needed.
  • An overall system approach to cooling that conforms to system form factor and reliability requirements will ensure that system cooling capability will not limit system performance.
  • Modularity and scalability will need to be built into various connector technologies used at the system level.

In conclusion, a number of advanced packaging technologies are available today to improve the performance of heterogeneously integrated IP on package. There is a focus on scaling interconnect densities in these technologies to help scale bandwidth between die-to-die links on package and to drive performance. Closer collaborations between package and system designers to optimize package system integration will help maximize system performance.

This article was originally published on EDN.

Ravi V. Mahajan is an Intel Fellow, is technology development co-director for Assembly and Testing Future Technology at Intel, and has worked on many microelectronics packaging technologies. He received the Ph.D. degree in mechanical engineering from Lehigh University, Bethlehem, PA, USA.

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