The RISC-V open-source hardware effort started as a project at UC Berkley, where the first RISC design happened to have been produced...
“Open Source” has multiple meanings in the context of hardware designs: an open specification, open/free design files/RTL, designs with expired patent/copyright protection, designs that were dumped when the sponsor decided to discontinue support—otherwise known as abandonware.
As such, the value of open-source hardware varies. Many original open-source hardware projects were small, with limited impact on the chip design business. While it is not the first open-source hardware project, probably the best-known and the one that has had he biggest impact on the industry is RISC-V (pronounced “risk five”).
RISC-V changed the game.
The open-source chip effort started as an academic project at University of California at Berkley, the same institution that produced the first reduced instruction set computer (RISC) CPU: the RISC-1. Among the architecture’s founders was David Patterson, who wrote the seminal research paper on RISC. RISC-1 went on to become the Sun Micro SPARC processor. In the 1980s, RISC illustrated how viable companies could be built around a new processor architecture.
RISC-V was originally intended as a teaching and research tool. The instruction set design was clean, simple, modern, free of IP entanglements. The open approach allowed researcher to build chips, extend the architecture, explore new instructions. It was also simple enough for graduate students to design.
The university team turned RISC loose in the public domain. Others began using it. The result was momentum among academics and researchers who built an ecosystem around RISC-V. The Berkeley team then forged a foundation to formalize development and seek community input. The earliest industry outreach occurred during the Hot Chips conference in 2014 with a tabletop display. Since then, the project has snowballed into an international movement.
The foundation became RISC-V International, which moved its headquarters to Geneva, Switzerland — symbolic of its neutral stance. RISC-V International CEO Calista Redmond describes RISC-V as an open standard architecture. The group also claims no specific CPU as an open-source design. Rather, it is an instruction set and behavioral specification that is developed to a point, then frozen.
RISC-V serves as a building block on which companies can add extensions. It’s up to the implementors to decide to release as open-source their CPU cores, to charge for use of cores, or a combination of both.
The standard is open, but the CPU designs built on the standard don’t have to be open or free. As an example of an open design, Western Digital developed SweRV cores for internal use in flash array storage controllers. It then open-sourced the cores.
Hence, RISC-V offers a low cost of entry, a new, cleaner architecture and architectural flexibility.
One concern is fragmentation of the RISC-V instruction set, but the base architecture is sufficient for standardized software development. The instruction set also can benefit from broad community involvement — there are 50 committees working on various aspects of the design and ecosystem.
Another advantage of the RISC-V open specification is eliminating the need for an architecture license, as users would be required for Arm or MIPS IP in designing their own CPU core. While Arm does offer some development cores for free, designers must still use Arm designed cores and pay a royalty on units shipped. Most commercial chips still use licensed cores.
Even if designers are willing to license a pre-made CPU, they have many more IP choices.
For example, Taiwan’s Andes Technology Corp. has developed licensable RISC-V cores. Several RISC pioneers founded SiFive to develop licensed, open-source, and customizable CPUs, although its business model is based on design services and delivering IP with commercial features such as trace, debug and security options. Much like the companies that profit from Linux distributions, including Red Hat and SUSE, design companies can profit from RISC-V by offering customized and supported CPU IP.
Technical sovereignty is another emerging IP issue, particularly with the rise of a technological Cold War. In the case of RISC-V, no one country controls the IP. Therefore, there’s no way to stop someone from using the instruction set based solely on trade disputes.
For now, the RISC-V ecosystem has also become the focus for other open-source designs. For example, a group called libreSoC is developing an open-source GPU based on RISC-V. The goal is a hybrid CPU, VPU and GPU.
Indeed, RISC-V is not the first open-source hardware repository. It was preceded by Open Cores, a site that allowed developers to “view, download, reuse, and share gateware designs.” Projects included actual circuit designs, but most are obscure academic projects or discontinued IP referred to as “left-over-wear” or “abandonware.” These cores lacked robust, extensible community support and were offered for hobbyist and academics pursuits.
The other open CPU architectures include IBM Power and Sun Microsystems/Oracle SPARC.
The OpenSPARC project began in 2005. A site distributed RTL for the SPARC T1/T2 cores released under a GNU General Public License. They were small, multithreaded cores good for throughput computing.
Another is the LEON CPU core developed for the European Space Agency. The 32-bit SPARC V8 core was available under two different licenses. Once Oracle ended SPARC development, interest in the architecture waned.
IBM launched the Open Power Foundation in 2013, along with partners Google, Tyan, Nvidia and Mellanox. The original goal was to offer an alternative to Intel’s processor dominance in servers and HPC. But there was a significant limitation to the project: IBM was originally the sole Power chip provider. Later, a Chinese company, Suzhou PowerCore, developed a Power processor. Interest in the project waned once Arm server and AMD Epyc processors entered the market to challenge Intel. Development continues, albeit slowly.
Last September, IBM contributed its A2O Power processor core, an out-of-order follow-up to the A2I core. The A2O is a 64-bit CPU with significant single-thread performance capable of 4-GHz clock speeds and based on a 7-nm process. The OpenPOWER project also spurred related interface standards projects such as OpenCAPI and OMI (Open Memory Interface).
Still, OpenSPARC and OpenPOWER have had limited impact. Even though offering “open” access to the architecture, the origin companies were slow to relinquished control to the design community. OpenPOWER designs are robust, but lack a complete platform, including a floating-point unit. Moreover, they remain highly dependent on IBM support.
More recently, a Linux Foundation initiative called the CHIPS Alliance, as in Common Hardware for Interfaces, Processors and Systems, has sought to seed the open-source hardware ecosystem. In December, the consortium announced plans to work with RISC-V International to standardize on an open, unified memory coherency bus aimed at data-heavy applications.
To be successful, open-source intellectual property needs a strong, diverse community behind it. Also needed is an open ecosystem that values contributions to the architecture while providing a clearinghouse for new developments. In this way, open-source IP projects can finally compete with licensed cores and proprietary architectures.
RISC-V projects exhibit most of these requirements, and are therefore most promising. OpenPOWER, too, has potential, but needs wider support to reach critical mass for market acceptance.
Still, the long-term success of RISC-V is not a given, and the world’s leading IP provider, Arm, is not going away anytime soon. Arm could undergo significant business model changes if its acquisition by Nvidia survives antitrust scrutiny. Nvidia has so far pledged to leave Arm’s business model intact.
It may still be possible for Arm to adopt a mixed IP licensing model, but extensions will likely be limited to the big architecture licensees like Apple.
Meantime, RISC-V will continue to attract more investment and talent. Much of the open-source architecture’s initial success has been in microcontrollers. As it moves up the performance stack to applications and data center processors, it will have to compete with an entrenched and extensive Arm ecosystem.