Novel Power Management Platform to Improve Efficiency

Article By : Maurizio Di Paolo Emilio

Tower Semiconductor has a new 180nm Power Management modular technology for power management integrated circuits up to 24 volts. This is the company’s 6th Gen process leads to improvements in energy efficiency...

Tower Semiconductor has a new 180nm Power Management modular technology for power management integrated circuits up to 24 volts. This is the company’s sixth generation (6Gen) process leads to improvements in energy efficiency (up to 35 percent from its previous process, the company claims), the minimization of form factors, and reductions in the number of production layers.

The power generation sector is trying to improve the efficiency and reliability of the power grid. At the power management IC level, the main parameters that are part of the technical specification are:  power transistor resistance, breakdown voltage, and robustness.

“The first parameter is defined as RDS(ON) (resistance between drain-to-source when the device is on), the lower the better,” said Erez Sarig, Tower’s director of power management business development and marketing. Breakdown voltage defines the voltage in which the device is breaking.  “As breakdown voltage increases, the RDS(ON) increases,” He added.

Robustness, instead, describes the performance of the device according to the application. “This is related to guaranteeing that devices will last for years without degradation in performance,” said Sarig.

In the power electronics ecosystem, we can identify four main challenges.

“The first challenge,” said Sarig, “is to have an aggressive power efficiency. The second,” he continued, “is the power density — meaning small size volume solution (for example in data centers the power consumption increases but the total area is limited in each server). The third is the need for integration of digital due to the need for more computation capabilities within power products for power delivery improvements and operation monitoring. At the end, the forth is cost pressure driven by the increased amount of power components in all products.“

Power Management wafers. [Source: Tower Semiconductor]

He continued “as a general statement, the main advantage provided by manufacturing on our advance technology is the possibility for a better performance and cost structure.” As energy consumption increases, system architectures rely on high-efficiency projects.

Tower Semiconductor’s power management platform offers high levels of functional integration including a wide range of memories, 1.8V and 5V high-density libraries, and advanced power LDMOS; all adaptable for a variety of applications such as mobile, wearable, industrial and automotive and growing computing worldwide.

The platform includes 180nm and 65nm bipolar-CMOS-DMOS (BCD) processes, and high voltage RESURF bulks 140V and 200V SOI technologies. Over 100 devices fit any power management project, including resistors, BJTs, capacitors as well as CMOS (and LDMOS).

“In most power products there is a need to integrate analog, digital, and power domain. The analog domain uses both bipolar and CMOS devices while the power domain uses the DMOS and bipolar devices, therefore using the BCD technology enables to offer a comprehensive solution answering the abovementioned requirements for better integration of digital, analog and power,” said Sarig.

Tower’s sixth-generation technology (Gen6) is based on existing, high-performance power management platforms and is largely backward compatible, allowing existing parts and designs to be easily transferred to the new, more efficient process.

“The Gen6, with its leading performance, leverages the power efficiency and form factor across a very wide variety of end-applications, for example, microprocessor voltage regulators with driving capabilities of tens of amperes, motor drivers, multi-channel PMIC, USB-C PD and more. This is as a result of the low Rds(on) and thick back-end that enables low power losses,” said Sarig.

A typical solution allows the possibility to reuse circuits with different isolation schemes offering the highest level of silicon optimization, fast time to market, and an efficient design cycle with significant cost savings.

Wafer fabrication [Source: Tower Semiconductor]

“The technology was developed using TCAD (technology computer-aided design) simulations and multiple silicon runs. The development of every technology requires extensive R&D work, time and other resources and we are very excited to offer it to our existing and potential customers,” said Sarig.

The Gen 6 process offers a profoundly lower RDS(on) with a record 6mΩmm² and a low number of production masks, allowing significant performance and cost benefits.

Minimizing RDS(ON) requires the appropriate chip technology as well as a package with low interconnection resistance. The interest in solutions with ever lower Rds(on) is a strong demand from the market. When selecting semiconductor switches, it pays to investigate the detail of datasheet specifications — especially how critical parameters like Rds(on) changes with temperature. RDS(on) is the total resistance in the path from source to drain, is made up of a series of resistances that traverses the path of current flow.

Robust design with high fault voltage under all operating conditions provides increased circuit reliability for high power monolithic integrated solutions in DC-DC, PMIC, and motor driver applications.

Tower Semiconductor at the end of February changed its name from TowerJazz.

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