Over the last few years, the industry has embraced the idea of measuring a process node by PPA—performance, power and area.
Instead of using a transparent benchmark, foundries have been naming their latest process nodes based on their desired market positioning. It's time the shenanigans stop.
Intel recently proposed a simple but somewhat self-serving density metric. The response from rival foundries was a deafening silence. I suspect that Intel has an edge in transistor density, something its competitors don’t want to admit.
Intel deserves praise for its recent decision to reveal metrics such as fin pitches and heights and minimum metal and gate pitches on its 10nm node, which has not yet started production. These are the kinds of basic details that all foundries should supply when they first announce a new node.
However, such metrics and the transistor density that can be derived from them are only part of the story. If you can’t deliver transistors that support significantly higher speeds or lower power consumption, it doesn’t matter how many of them you can deliver.
Back in 2009, ARM chief technologist Mike Muller coined the term dark silicon. Engineers are packing more transistors on a die but lack the power budget to turn many of them on, he observed.
Intel’s density metric is good as far as it goes, but without related formulas for performance and power, it fails to tell the whole story. Over the last few years, the industry has embraced the idea of measuring a process node by PPA—performance, power and area.
The consulting firm International Business Strategies (IBS) suggests using a metric of “effective gates … [that] takes into account available gates, [what Intel’s metric reports, as well as] gate utilisation and yields,” said IBS chief executive, Handel Jones. “While available gates are useful … it is only the tip of the iceberg.”
The trouble is, “companies are very secretive regarding yields … but cost per gate … is the critical metric and is impacted by D0 as well as parametric and systemic yields” and how long it takes for customers to get chips, he added.
Several EE Times readers provided their thoughts on a metric in comments on our story on Intel’s proposal.
One reader called for a measure of RC time delay in nanoseconds per mm2 “if we use capacitance and resistance per unit length.” Another reader suggested that Intel’s metric is not useful because it does not include information on standard cell tracks.
Another reader said, “The real measure is how well the process plus the libraries work together across a range of design types [and] performance criteria. I would like to see Intel libraries and process vs. ARM/TSMC libraries [and process] compared on real synthesisable designs like a large ARM core complex/SoC and a large x86 core, targeted at the same clock rates.”
Several readers agreed that the final roof of the pudding arrives long after the node itself in the competitive stats and sales of chips made in the process. They also observed TSMC and Samsung are ramping chips in what they call 7nm processes this year as Intel ramps what it calls its 10nm node.
Analyst Linley Gwennap said that Intel’s density metric “must be combined with SRAM cell size to get a full picture of SoC size, particularly for processors that include large amounts of memory” and called on foundries to provide more data on their process nodes.
Figure 1: IBS suggests that chip designers need to consider a table of metrics. (Source: IBS)
More options heighten the confusion
The industry needs a foundry metric more than ever. In March, TSMC announced a trio of new nodes—22nm, 12nm and 7+nm in addition to multiple existing 16nm nodes and a 10nm node that it is ramping this year. The world’s largest pure-play foundry aims to cover all the bases with options that sometimes squeeze out improvements measured in single digits.
Meanwhile, Globalfoundries has sparked a feeding frenzy in the sweet spot of its 22nm fully deleted silicon-on-insulator process. It even attracted Intel to take a couple of steps back from its preferred position on the bleeding edge to announce a low-power 22nm FinFET process.
The top foundries will probably start using extreme ultraviolet lithography by about 2020. Initial processes using EUV may exhibit fine difference as foundries come to grips with ways to use this critical new tool.
Fabless chip designers need a clear way to compare the pros and cons of their growing set of options. The sector’s otherwise active trade and industry groups don’t appear to have any efforts in this area. It’s a big gap that the Global Semiconductor Association (GSA), SEMI or the IEEE could address.
As the representative of fabless chip designers, the GSA in particular ought to grab this flag and run with it. Ironically, I received no response after reaching out last week to three GSA representatives.
I understand that this is a hotly competitive area and, thus, rife with corporate trade secrets. So far, Qualcomm declined to provide an interview on how it compares process technologies. Nvidia and Mediatek, so far, have failed to respond to my requests.
I’m not surprised. They can gain a strategic advantage that they don’t want to give away by picking a process node wisely.
In many cases, business criteria may weigh nearly as heavily as technical ones.
When Apple chose TSMC to make its applications processors, Samsung lost orders for tens of millions of units annually. Interestingly, at about that time, Qualcomm began making many of its Snapdragon SoCs in Samsung’s 14 and 10nm processes, and Samsung became the first handset maker to use the 10nm Snapdragon 835 in its Galaxy S8 smartphone.
Making semiconductors involves some of the most complex techno-business decisions in high tech. Their implications ripple across broad systems, software and services markets around the globe.
The industry needs a few public benchmarks to make sense of the growing proliferation of choices. Foundries need to be held accountable to deliver the data to fill in those metrics.
Intel provided a start with its recent 10nm disclosure and density proposal. Other major foundries need to follow suit and go one big step further by providing related performance and power benchmarks to go with it.
I don’t expect that the foundries will do this unless they come under real pressure. The ball is in the court of a group like the GSA or anyone else who wants to step up to the microphone to end the deafening silence.
First published by EE Times U.S.