The six-track 12nm FinFET process is an upgrade for midrange mobile and video processors and high-end IoT devices using 16FFC, according to TSMC.
TSMC plans a six-track 12nm FinFET process that falls between its 22nm planar and 10/7nm FinFET nodes. It sees it as an upgrade for midrange mobile and video processors and high-end IoT devices now using its 16FFC process. High end GPUs and FPGA are using a 16FF+ variant and will migrate to 10/7nm.
The 16FFC process which has had eight design wins is not yet in volume production. The 12FFC process should start risk production before June and deliver 1.1x the speed or 0.7x the power of 16FFC process.
Compared to 16FFC, 12nm chips running at less than 2.4GHz could see 20% area shrinks. Those running faster than 2.4GHz could be optimised for an additional 6% in speed gains.
The 12nm process uses the same design rules, masking layers, SRAM cell layouts, voltage ranges and I/O devices as 16FFC. Like the 22nm process, designers can mainly re-characterise SRAM, analog and I/O components from the prior node.
An ultra-low power version of 12FFC will support 0.5V operation.
Separately, TSMC described RF variants of processes ranging from 28nm to 12nm. They aim to serve a wide range of products including 5G radios operating in millimetre bands. It positioned a 22nm ULP variant against 22nm FD-SOI.
In packaging, TSMC is developing multiple versions of its InFO process, one for HPC supporting substrates as large as 65mm2. An upgrade of TSMC’s 2.5D CoWoS process will support stacks of as many as eight DRAMs using HBM2 on substrates up to 1500mm2.
Meanwhile in its R&D labs, TSMC has built next-generation transistors out of horizontally stack gate-all-around nanowires. It has also demonstrated the structures using germanium. The company also mentioned work in new interconnects and a back-end capping process, all aimed at enabling nodes at and beyond 3nm.
Finally, TSMC will deliver late this year a machine-learning capability for limited functions on ARM A72 and A73 cores. The capabilities include predicting optimal cell clock-gating to bolster overall chip speeds 50-150MHz.
The techniques use training models maintained by TSMC using open source algorithms such as Caffe. Designers will be able to create custom scripts they keep privately. Ultimately the service will span more processor types and functions.
First published by EE Times U.S.