Synopsys has teamed up with TSMC to develop an IP portfolio for TSMC's 12nm FinFET process. The DesignWare Interface, Analog and Foundation IP will help designers accelerate development of mobile SoCs that incorporate logic libraries, embedded memories, embedded test and repair, USB 3.1/3.0/2.0, USB-C 3.1/DisplayPort 1.3, DDR4/3, LPDDR4X, PCI Express 4.0/3.1/2.1, SATA 6G, HDMI 2.0, MIPI M-PHY and D-PHY and data converter IP, according to the company.

TSMC has already certified Synopsys's Galaxy Design platform for its 12nm FinFET process. The 12nm certification brings with it the broad body of design collateral, including routing rules, physical verification runsets, signoff-accurate extraction technology files, SPICE correlated timing and interoperable process design kits (iPDKs) for this latest FinFET process. Synopsys Custom Compiler design solution support is enabled through an iPDK, according to the company.

To accelerate access to the power-efficient, high-density process, IC Compiler II place-and-route system has been enabled to support new standard cell architectures seamlessly co-existing with 16FFC IP.

Recent collaborations between the two companies have resulted in enhancements to IC Compiler II's core placement and legalisation engines ensuring maximum utilisation while minimising placement fragmentation and cell displacement, according to Synopsys. The 12nm ready iPDK enables designers to use Custom Compiler's layout assistant features to shorten time in creating FinFET layouts.

Synopsys's DesignWare IP for USB 2.0/3.0/3.1/Type-C, DisplayPort, PCI Express 4.0/3.0/2.0, SATA 6G, MIPI D-PHY/M-PHY, 25G Ethernet, HDMI 2.0, DDR4/3 and LPDDR4X, and 12-bit data converters are expected to be available for TSMC's 12FFC process in Q3 2017.