Using the new 3D Network-on-Chip (3D-NoC) technology, researchers at Leti, a CEA Institute, have developed an on-chip communications system that it says substantially boosts computing performance while reducing energy consumption. Leti researchers accomplished this by stacking chips in a single enclosure, or by placing the chips side by side on a silicon interposer.

Asked about the new 3D-NoC technology’s demonstrator, Olivier Faynot, microelectronic component section manager at Leti’s Silicon Component Div., told EE Times, “Its layout is done, it’s now in foundry.” Once chips are fabricated at a foundry, they will be assembled at Leti, he said. “We will get silicon out in the fourth quarter of this year.”

Quest for 3D ICs

The chip industry’s quest for 3D ICs has come a long way in the advance of 3D integration technology. Successful examples of 3D ICs today include imagers, 2.5D interposers and 3D memory cubes.

Leti has been also pursuing the development of advanced 3D technology bricks (TSVs, μ-bumps, hybrid bonding, etc.), and designing advanced 3D circuits as pioneer prototypes.

The French research institute disclosed its first version of 3D NoC demonstrator in a paper submitted to ISSCC earlier this year.

In that paper, Leti researchers presented a homogeneous 3D circuit composed of regular tiles assembled using a 4×4×2 network-on-chip, using robust and fault tolerant asynchronous 3D links. The demonstrator provided 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.

The second version of Leti’s 3D-Noc technology, unveiled this week, is called INTACT (which means “ACTive INTerposer.”)

The new 3D circuit combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer. The active interposer integrates several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components, according to Leti’s announcement.

Leti 01 Figure 1: (Source: CEA Leti)

Leti’s latest 3D IC project demonstrated that with 3D technologies and through silicon vias (TSV), it’s possible to stack various dies together. This development “opens a full scope of new application possibilities,” said Faynot. In short, you can integrate more devices from potentially different technologies (CMOS, MEMS, DRAMs, etc.), he explained.

In the second-generation 3D NoC technology, Leti used FD-SOI and co-integrated it on a CMOS interposer, because those processes were available, explained Faynot. “But in theory, you can use different process technologies—bulk CMOS or FinFET, as you like.”

Full 3D can be envisioned by stacking dies vertically on top of each other, or in interposers—also called 2.5D—stacking dies horizontally onto a silicon substrate, said Leti.

Reducing distance

Leti began its 3D IC projects by looking for an architecture to connect main memory to large numbers of processors in a multicore processing engine, explained Faynot.

In recent years, as chips have gotten more complex, their die size has gotten bigger. As a result, the distance between processing cores and memory—where data needs to travel—has also gotten longer. Distance matters because it results in a higher cost for data movement, Faynot explained.

The researchers initially tried to stack in 3D a large number of homogeneous logic dies, seeking to reduce the distance between processors and memory.

But with Moore’s law pushing more advanced nodes, the yield of large dies has kept going down. The lower yield rate has led to high-end large dies that cost too much.

So, Leti researchers tried the idea of partitioning a larger single die in smaller dies (smaller dies mean better yield) and assembling them in 2.5D using interposers.

Leti 02 Figure 2: (Source: CEA Leti)

They are now splitting a multi-core system in multiple chiplets stacked onto a larger active interposer. This leads to yield optimisation, Faynot explains, as chiplets are composed of computing processing units, fabricated in advanced technology, pre-tested and assembled on a large size interposer, fabricated in a mature technology.

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