Fujitsu’s referenceless CDR cuts down optical modules’ power to 70%, enabling high traffic transmission through denser implementations.
The University of Toronto and Fujitsu have announced a joint development of power referenceless CDR. The circuit operates with 55% of the power requirements for optical modules in Ethernet used for communication between servers and switches in data centres. With the spread of big data analysis and cloud services, faster and denser optical modules were necessitated, thus calling for the miniaturisation and reductions in power consumption.
To speed up and miniaturise optical modules, referenceless CDR technology has been developed with new timing-extraction technology that can operate on the same cycle as the data transmission speed, sans the crystal oscillator. The result is that the number of timing generators can be reduced to a quarter–cutting the optical module‘s power consumption about 70%. Lower power consumption of optical modules enables high traffic transmission capability through denser implementations and thereby improving data centre processing capability.
Reducing the number of components like the standard timing (reference) and the crystal oscillator in optical modules is an effective way to reduce the power consumption and improve miniaturisation.
Figure 1: Illustration shows between a CPU and an optical module using referenceless CDRs.
Figure 2: Diagram shows existing referenceless CDR and frequency difference detection. When the crossover point is observed to change from A→B→C→D, it can be understood that the data-reading cycle is shorter than the input signal. If the opposite change, from D→C→B→A, is observed, it can be understood that the data-reading cycle is longer than the input signal.
With this technology, in order to detect discrepancies in the data-reading cycle from amplitude information, three decision circuits with different threshold levels (low, medium, and high) determining whether the input signal is a 0 or a 1, all operate at the same timing to investigate the change in the input signal.
The input signal is observed with respect to clocks 1 through 4-generated by the timing generators-as it changes from 0 to 1, and each bit is assigned a 1 or a 0. This makes it possible to observe between which two clocks the data changed from 0 to 1 or vice versa.
Figure 3: When the input signal changes from 0 to 1, if the three results determined by the timing of clock 1 are "0,1,1", then it can be determined that the point at which the input signal changed is earlier than the determination timing of clock 1 (yellow area ), while if the results are "0,0,1", then it can be determined that the point at which the input signal changed is later than the determination timing of clock 1 (green area). Then, by investigating how that timing is changing, timing discrepancies can be detected.
Figure 4: An illustrative configuration for referenceless CDR technology where it becomes possible to reduce the number of timing generators to one fourth that of previous architectures.