The solution enables earlier narrowing down of process and device options to reduce expensive and time-consuming wafer-based iterations, and also allows the creation of higher-quality early Process Design Kits for design technology co-optimisation.
A pre-wafer simulation solution from Synopsys promises to help semiconductor manufacturers reduce process node development time.
In the past, the development of new process nodes was focused on the scaling and optimisation of single device architecture, the planar MOSFET, and a single material, silicon. With the introduction of FinFET in logic and 3D NAND in memory, the complexity of new process nodes increased significantly. This complexity will only accelerate as future process nodes will need to evaluate and select among a larger number of processes, device architectures and materials.
"To meet the performance, power, area and cost targets of the 10nm process node and beyond, semiconductor manufacturers need to evaluate a larger number of process options, device architectures and materials, and account for design criteria in selecting the best options," said Dr. Anda Mocuta, Director of Technology Solutions and Enablement at imec.
Synopsys's new solution provides a comprehensive process, transistor and circuit simulation flow that enables technology development and design teams to evaluate various transistor and process options using a design technology co-optimisation methodology that starts in the pre-wafer research phase. The generation of SPICE models, design rules and parasitics from TCAD and lithography simulations allow the creation of early process design kits to evaluate the performance, power, area and cost of a new process node.
According to Mocuta, the simulation solution "enables seamless links in the DTCO chain and helps speed up the down-selection of technology options."