Compared to the Tensilica Fusion F1 DSP, Fusion G3 DSP shares the same base Xtensa ISA, while adding richer and higher-throughput DSP instructions.
The latest IP release from Cadence-Tensilica builds DSPs programmable in C/C++ with near-optimal performance out-of-the-box, multi-purpose fixed and floating point VLIW DSP, comprehensive data-type support with auto-vectorisation, as well as real-time control with flexible memory subsystem, integrated DMA controller and memory protection unit.
A multi-purpose, high-performance DSP for compute-intensive SoC designs, Cadence presents the Fusion G3 DSP as exceptionally easy to program for use in automotive, consumer, Internet of Things (IoT) and industrial applications that combine intensive audio, imaging, communications, radar and embedded DSP computation.
“As we continue to broaden our customer base, we are solving a wider range of SoC challenges. The flexibility of the new Tensilica Fusion G3 DSP is perfect for customers running a diverse set of software applications,” stated Steve Roddy, senior group director of product marketing for Tensilica in the IP Group at Cadence. “With advanced development tools including auto-vectorisation and extensive library support, the Tensilica Fusion G3 DSP provides our customers with an easy development flow and higher performance out-of-the-box for their next-generation applications. Even those with extensive floating-point performance requirements can quickly port existing code to the Tensilica Fusion G3 DSP with the optional Vector Floating-Point unit.”
The Tensilica Fusion G3 DSP expands on the multi-purpose Tensilica Fusion DSP product family introduced in 2015. When compared to the Tensilica Fusion F1 DSP, the Fusion G3 DSP shares the same base Xtensa instruction-set architecture (ISA), while adding richer and higher-throughput DSP instructions. Suited to more compute-intensive applications including radar, imaging and mid- to high-end audio pre/post-processing, it delivers this performance with quad 32-bit integer MACs and quad single-precision 32-bit floating-point MACs.