Co-optimisation tools are now becoming mainstream to help translate between different worlds of chip designers and lithographers.
For some time, engineers have been talking about using EUV to print just a few critical layers on chips in fabs that generally use armies of existing steppers. The SPIE Advanced Lithography conference was host to some of the first public descriptions of such efforts.
ASML’s road map includes light-source upgrades, in part because it knows that users need headroom to make up for underperforming resist chemicals and optics that will degrade over time. But the company is mum on just how and when those upgrades will arrive, presumably because it has not yet gotten consensus among its handful of top customers.
New optics from Zeiss are the central focus of the new scanner. Other components, including the light source, will have evolutionary upgrades.
Figure 1: Carl Zeiss described a prototype system that it has already shipped, although a final version may not be available until late 2018. (Source: Zeiss)
Zeiss has already started ordering some components and building new grinding machines for the human-sized optical module. It requires two new inspection systems, also human-sized, that, for the first time, sit inside the vacuum chamber.
Unlike the 3400, the new system will expose two 16.5mm x 26mm half-sized fields at a time. That’s because it uses separate magnification levels on the x- and y-axis. To hit throughput targets, it will move through the system wafers at twice and masks at four times the acceleration rate of the 3400.
The system will have a 30nm focus budget, half that of the 3400B. It aims to start commercial life kicking out more than 180 wafers/hour while printing pitches from 22nm to 14nm. The system is also being designed to deliver EUV light doses up to 60mL/cm2.
Figure 2: Globalfoundries achieved cross-platform performance comparable to using various kinds of immersion tools but also discovered the limits of some correction techniques.
Globalfoundries described work processing five lots of 20 wafers each over two weeks using NXT:1970Ci and NXE:3300B scanners at its Malta, New York, fab. It achieved cross-platform performance comparable to using various kinds of immersion tools but also discovered the limits of some correction techniques.
Nevertheless, the company said it is “very likely” that EUV will be used for selected layers in a volume 7nm process. Presumably, the move would come in a roughly 2020 upgrade to the 7nm process it said in September that it expects to roll out in 2018.
Separately, a research institute is already working on the definition of a 3nm node using double-patterning EUV. A Synopsys engineer described work modelling the process using co-optimisation tools that he said are now becoming mainstream to help translate between the increasingly different worlds of chip designers and lithographers.