Semiconductor companies ramping up design capabilities for emerging 7nm processes are facing increasing test quality and yield management challenges. To address this, Synopsys has expanded its test and yield analysis solution targeting FinFET-specific defects to enable higher quality testing, repair, diagnostics and yield analysis of advanced 7nm SoCs.

To improve defect coverage, Synopsys has been collaborating with several semiconductor companies to advance testing and diagnostics methods for logic, memory and high-speed mixed-signal circuits targeted for manufacture with 7nm processes. These collaborations are enabling rapid deployment of new functionality within Synopsys' synthesis-based test solution, featuring TetraMAX II ATPG, DesignWare STAR Memory System and DesignWare STAR Hierarchical System.

For logic circuits, new modelling techniques, such as resistance sweeping, improve the ability of slack-based cell-aware tests to detect defects such as intra-cell partial bridges that are more prevalent with advanced FinFET processes. For embedded memory test and repair, the STAR Memory System solution incorporates custom algorithms based on silicon learning at foundries to detect and repair defects exemplified by resistive fin shorts, fin opens and gate-fin shorts. Furthermore, the DesignWare STAR Hierarchical System enables high coverage manufacturing and characterisation test patterns for the 7nm DesignWare PHY IP to be efficiently applied through the SoC hierarchy.

To accelerate diagnosis of 7nm yield issues, defect isolation to specific areas within design cells is possible through new support of cell-aware descriptions in the database shared between TetraMAX II ATPG and Yield Explorer solutions. The combination of test and diagnostic advances increase 7nm defect detection and speed up failure analysis and yield ramp in production manufacturing environments.

"The growing complexity and process variation found with advanced 7-nm FinFET processes requires improved test and yield technologies," said John Koeter, vice president of marketing for IP and prototyping at Synopsys.