Smoltek's core technology platform, SmolGROW is what the company claims to be the only process that enables controlled growth of conductive nanostructures at 390°C using CMOS compliant materials and processes. With this low-temperature CNF growth well under control, the company has secured an IP portfolio covering a number of applications including dense 2.5/3D stacking (SmolINPO), ultra-fine pitch interconnects (SmolINCO), integrated capacitors for energy storage or decoupling (SmolCACH), but also thermal interface materials (SmolTIM) for high performance RF and power electronics components and SmolNIL, making use of the CNFs to fabricate high aspect ratio structures through nano imprint lithography (the CNFs have a typical diameter of 50 to 100nm, being from 2 to 150 micrometres long, depending on process parameters).

Contemplating an IP licensing business model, Smoltek's Chief Innovation Officer & Founder Dr. M. Shafiq Kabir shared his insights with EETimes Europe.

"We will licence our IP to both OSATs and foundries so they can offer the process to their customers on top of silicon, either to integrate new discrete components like our SmolCACH, or to integrate the CNFs in new packaging strategies" Kabir said in an interview.

news-smoltek-1 Figure 1: *A forest of CNFs grown onto a metal IC bond pad. (Source: Smoltek) *

"We are also working on a Process Design Kit (PDK) for the vertical integration of our process into the IC design flow, because everyone has to be aligned to optimise IC and package integration".

The CIO revealed that his company was engaged in small projects with a number of customers, to do mostly with miniaturized interconnects exploiting the high thermal and electrical conductivity of CNFs to boost traditional micro-bumps (with copper wetting and anchored onto CNF patches).

"You could find our IP in commercial applications within the next two to three years" he said.

"With this technology, we are not aiming at replacing Through Silicon Vias (TSVs) yet, but we'll solve the TSVs/interposer bottleneck. Copper micro-bumps don't scale too well", Kabir explained, "copper electro-migration impacts the lifetime reliability of silicon dies, and only CNF-based bumps will be able to scale down with future nodes".

In a whitepaper "Using carbon nanostructures as the assembly platform in semiconductor advanced packaging beyond Moore," the company mentions the use of selective electroplating, based on the conductive properties of CNFs to further reduce bump pitch without relying on micro solder balls. It sees a potential for 3D-shrinkage orders of magnitude (>10x-100x) compared to existing and well established bump/pillar technologies. This would allow bare dies to be stacked on each other or bonded to a substrate (interposer) or carrier (lead-frame) with much higher density interconnects.

news-smoltek2 Figure 2: (left) nanostructures grown in “checker box” pattern, (right) an array of nanostructures grown on a substrate. (Source: Smoltek)

An interesting ongoing development which could interest many OSATs doing Integrated Passive Devices (IPDs) for their customers is the SmolCACH (Capacitor on Chip) Smoltek is working on.

"For the moment we have achieved capacitors with moderate values in terms of capacitance per unit area for the solid state version. However the electrochemical devices show very promising results. The actual values are to be published and we'll have to wait for some final reviews by our tech team" commented Kabir, accepting to share with us a SEM photograph of a newly manufactured ‘all solid state’ test mini supercapacitor. The SEM photograph shows a carpet of vertically grown CNFs sandwiched between two electrodes.

news-smoltek-3 Figure 3: SEM photograph of a newly manufactured ‘all solid state’ test mini supercapacitor. (Source: Smoltek)

"The process involves a number of lithography and materials depositions, so you may be seeing some shadows of those different layers", commented Kabir about the faint square patterns within the rectangular shape.

"This particular device has just came out of the lab and has yet to be measured and analysed. However, we have seen an increase of a factor of 5 to 10 of the capacitance per unit area (footprint) compared to the planar counterparts in our first non-optimised version. This new batch is coming out of the lab after some optimisation and we will see what it will give us" the CIO said when pressed for some characteristics.

"We are always striving to get the best values out through different technical optimisations. Some target values for performances benchmarking include over 500nF/mm2 in DC with a breakdown voltage to be superior to 2V, and over 1nF/mm2 with a breakdown voltage over 25V for RF applications".

Last year, Smoltek's co-founder Prof. Peter Enoksson from Chalmers University of Technology (Gothenburg, Sweden) published a paper in the Solid-State Electronics journal "CMOS compatible on-chip decoupling capacitor based on vertically aligned carbon nanofibres", presenting on-chip decoupling capacitors of specific capacitance 55pF/µm2, 10 times higher than commercially available discrete and on-chip decoupling capacitors at the 65nm technology node, the paper claimed.