Samsung is starting to make chips in a 5nm EUV process, but gains are less impressive than past foundry nodes
SAN JOSE, Calif. – Samsung announced it has completed work and is taking orders for a 5nm foundry process using extreme ultraviolet lithography. It will offer 25% greater density and either 10% more performance or 20% less power consumption than its 7nm node with EUV announced in October.
Samsung has taped out “many” 7nm chips as well as one device in a so-called 6nm node that lets users make custom changes to its 7nm process and IP blocks. It also announced plans to start production in 2020 on a second EUV foundry line it is now setting up next to its current S3 line in Hwaseong, Korea.
With the news, the Korean giant aims to steal some thunder from larger rival TSMC, which is scheduled to give an update on its work on a 5nm node next week. The two are racing to capture a lucrative but shrinking market for leading-edge process technology at a time when it’s becoming more complex and costly to make chips smaller and faster.
Samsung declined to share line widths and pitches used on its 5nm node or relative costs of the new process.
“We’ve been using EUV on 7nm mostly in the back end, but for 5nm we are adding a little more [use of EUV] to the middle of the line,” said Shawn Han, a senior vice president for Samsung’s foundry group. “We are in a leadership position for EUV productivity,” he added, declining to share specifics about EUV wafer throughput, uptime or defect levels.
“All the teams in the industry are working to secure the [best] source power, defect-free masks and enhancements in materials for [EUV] photoresists…Our advantage is we have in-house mask-making facilities where we’ve been building up know-how,” Han said.
In October, Samsung said it’s EUV throughput was at or above 1,500 wafers/day. It’s light source delivered a 250W sustained performance and a 280W peak, though it targeted 300W.
The 25% density gain and 10% performance boost or 20% power decline for the 5nm process marks a relatively minor advance. In October, Samsung said its 7LPP process would deliver up to a 40% shrink and up to 20% higher speeds or 50% lower power consumption compared to its 10nm node.
TSMC said to have top fabless players at 5nm
Samsung declined to list the number and types of IPs it has available for 7nm, although it said they can all work unchanged at the 5nm node.
Following the footsteps of its Taiwan rival, Samsung plans an event in October at its North America headquarters where it will detail more offerings from its third-party IP and EDA partners. It also plans a May event in Silicon Valley where it will share its progress on fully depleted SOI, embedded MRAM and other specialty nodes and blocks.
TSMC and Samsung are in a close race at leading-edge nodes. However, TSMC has a much larger capacity and set of IP offerings.
Last year, TSMC had foundry sales of about $34.2 billion compared to $10.4 billion for second-place Samsung, both up 6% over 2017, according to market watcher IC Insights. While TSMC covers the waterfront of processes and markets, Samsung has been more focused, especially at the leading edge.
“We’re focusing on mobile like 5G and high-performance computing as well as AI—and we’re trying to move into automotive,” said Han.
At the 5nm node, “Samsung and TSMC are very close from the perspective of transistor density, performance and power. Samsung could be 3-4% percent better in performance and power, but it depends on the skills of the design engineers,” said Handel Jones, president of International Business Strategies.
Samsung has competitive manufacturing technology but TSMC has a better design ecosystem and packaging support, he said.
“The key issue for Samsung is that AMD, Apple, HiSilicon, Nvidia, Qualcomm and others are collaborating with TSMC at 5nm. Samsung needs an edge over TSMC, and it also has to increase its packaging support for mobile applications,” he added.