SAN JOSE, Calif. — The semiconductor roadmap could extend a decade to a 1-nm node or it could falter before the 3-nm node for lack of new resist chemistries. Those were some of the hopes and fears that engineers expressed at an evening panel session at an annual lithography conference here.

The session was intended as a lighthearted send-up of the long-predicted death of Moore’s Law. It also showed the disturbing uncertainties that are natural outgrowths of the many challenges perpetually appearing on the path to next-generation chips.

Today, Samsung has started production of 7-nm devices using extreme ultraviolet lithography. TSMC expects to ramp a 7+-nm node using EUV by June. ASML aims to serve both with a 2019 upgrade of its EUV system, the 3400C, promising throughput of 170 wafers/hour and 90+% availability.

One of the next big challenges is brewing more sensitive resist materials for the 3-nm node. Today’s chemically amplified resists (CARs) “are OK for the current and maybe next generation, but we’d like new platforms,” said Tony Yen, a vice president at ASML.

Yen pointed to the long history of CARs dating back to the 1980s and 248-nm lithography. “It’s about time we put more emphasis in new platforms like molecular resists,” Yen said.

With a total market for the crucial chemicals valued at less than a billion dollars a year, “the model needs to change,” he added. “Development could be done in a pre-competitive place and then licensed to commercial resist vendors.”

Ryan Callahan from resist maker FujiFilm disagreed. “There is great competition to secure the business because those who are first will succeed and others will be gone … [but with the] market getting smaller as some [such as GlobalFoundries] abandon EUV, resist suppliers won’t do consortia for developing together,” he said.

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ASML plans to release this year an upgrade of its current EUV system. Click to enlarge. (Source: ASML)

In an effort to jumpstart work on resists for next-generation EUV systems, imec and laser specialist KMLabs announced that they will form a so-called AttoLab. It will try to characterize how resists absorb and ionize photons in time frames measured in pico- and attoseconds.

“We will learn how to see the fine detail of radiation chemistry, working with suppliers to find new materials to take us to the next level … We will also look at quantum phenomena … it is pure science, but new technologies may come from this work,” said John Petersen, a principal scientist at imec who co-authored papers describing the new lab.

The resists are one way to reduce random errors known as stochastics, an old problem but one raising its head aggressively as engineers push toward the 5-nm node. Yen was bullish that ASML will deal with the defects that threaten yields.

“Stochastics are more severe now than they were with 193-nm lithography, but they can be countered by higher [light] doses,” Yen said. “Our roadmap goes to 500-W systems, so we are going up in power, and High NA systems will deliver a better image quality, so we are well-prepared to combat stochastics.”

Phillipe Leray, a metrology specialist at imec, was less optimistic. “We have to tackle the defect challenge in the near future,” he said. “Time is running out, and I don’t see any solution around the corner.”

Pulling out all the stops for scaling

Designers are gearing up to compensate for the possibility that perhaps one in a billion physical contacts in a logic chip will be bad, said Rob Aitken, a fellow at Arm. “There are several candidate methods to deal with it,” he said.

Aitken was among several on the panel who called for more focus on 3D structures given the success of chip stacks. The technique calls for a “new microarchitecture because the complexity of what you can design in 3D is vast, and no one has pursued it much beyond noting [that] power and clocking will be hard,” he said.

Separately, he said that designers are already gearing up for the move from 12- and nine-track standard cells to ones using just four tracks to enable scaling. “This was impossible a few years ago, but it’s possible now,” he added.

Indeed, the challenges are so steep that engineers are widening the scope of solutions they are considering in every area of chip technology. “We are looking at just about everything in advanced patterning,” said consultant Erik Hosler, noting that EUV emerged from the advanced patterning section of the conference that he now helps oversee.

“Last year, we included MEMS and MOEMS, and we will keep expanding to quantum to make this a place to ask questions … Lots of great things are going on and something will emerge,” said Hosler, a former EUV specialist at GlobalFoundries.

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Engineers have made significant progress delivering finer features with EUV. Click to enlarge. (Source: ASML)

The chip roadmap has long been a place where engineers grope in the dark for solutions. For example, today’s test systems can’t claim accuracy so they focus on consistency, said Leray of imec.

“Metrology is the biggest fear I have given the difficulty of direct inspection … [but] there are a lot of wavelengths we haven’t explored,” he said.

All panelists agreed that moving to 450-mm wafers and 9-inch reticles is one of the few areas not worth pursuing given the cost and limited payback. “We had an extensive 450-mm effort years ago, but you need a whole ecosystem, and without it, we won’t drive that change,” said Rich Wise, a technology manager at Lam Research.

In the end, the two moderators for the session took frank but upbeat positions.

“We are making progress, but we can extrapolate to where features are less than the diameter of a silicon atom, so lithography-driven scaling will come to an end,” said Harry Levinson, a lithographer with AMD and GlobalFoundries for more than 30 years.

“Limits do exist, but the best way around them is to change the paradigm,” said Chris Mack, a veteran consultant and author on lithography. “The brick wall is often in our own minds — innovations can move it and then we repeat the process of pushing.”